Chip design for high-performance DSP

Advances in silicon technology have been a key development in the realisation of many telecommunication and signal processing systems. In many cases, the development of application-specific digital signal processing (DSP) chips is the most cost-effective solution and provides the highest performance. Advances made in computer-aided design (CAD) tools and design methodologies now allow designers to develop complex chips within months or even weeks. This paper gives an insight into the challenges and design methodologies of implementing advanced highperformance chips for DSP. In particular, the paper reviews some of the techniques used to develop circuit architectures from high-level descriptions and the tools which are then used to realise silicon layout.

Assessment of fibre orientation in ultra high performance fibre reinforced concrete and its effect on flexural strength

Fibre distribution and orientation in a series of round panel specimens of ultra high performance fibre reinforced concrete (UHPFRC) was investigated using electrical resistivity measurements and confirmed by X-ray CT imaging. By pouring specimens in different ways, the orientation of steel fibres was influenced and the sensitivity of the electrical resistivity technique was investigated. The round panels were tested in flexure and the results are discussed in relation to the observed orientation of fibres in the panels. It was found that the fibres tended to align perpendicular to the direction of flow. As a result, panels poured from the centre were significantly stronger than panels poured by other methods because the alignment of fibres led to more fibres bridging the radial cracks formed during mechanical testing.

Influence of aggregate and curing regime on the mechanical properties of ultra-high performance fibre reinforced concrete (UHPFRC)

A new generation of concrete, Ultra-high performance fibre reinforced concrete (UHPFRC) has been developed for its outstanding mechanical performance and shows a very promising future in construction applications. In this paper, several possibilities are examined for reducing the price of producing UHPFRC and for bringing UHPFRC away from solely precast applications and onto the construction site as an in situ material. Recycled glass cullet and two types of local natural sand were examined as replacement materials for the more expensive silica sand normally used to produce UHPFRC. In addition, curing of UHPFRC cubes and prisms at 20 degrees C and 90 degrees C has been investigated to determine differences in both mechanical and ductility.

High performance VLSI architecture for division and square root

A novel high performance bit parallel architecture to perform square root and division is proposed. Relevant VLSI design issues have been addressed. By employing redundant arithmetic and a semisystolic schedule, the throughput has been made independent of the size of the array.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

Systolic building block for high performance recursive filtering

A novel bit level systolic array is presented that can be used as a building block in the construction of recursive digital filters. The circuit accepts bit-parallel input data, is pipelined at the bit level, and exhibits a very high throughput rate. The most important feature of the circuit is that it allows recursive operations to be implemented directly without incurring the large m cycle latency (where m is approximately the word length) normally associated with such systems. The use of this circuit in the construction of both first- and second-order IIR (infinite-impulse-response) filters is described.

Algorithms and architectures for high performance recursive filtering

Recently, a number of most significant digit (msd) first bit parallel multipliers for recursive filtering have been reported. However, the design approach which has been used has, in general, been heuristic and consequently, optimality has not always been assured. In this paper, msd first multiply accumulate algorithms are described and important relationships governing the dependencies between latency, number representations, etc are derived. A more systematic approach to designing recursive filters is illustrated by applying the algorithms and associated relationships to the design of cascadable modules for high sample rate IIR filtering and wave digital filtering.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.