Providing a healthcare input to children in special schools

The education of children with speical educational needs is often accompanied by a requirement for medical or healthcare provision. If this cannot be done safely then the child's access to education may be limited. No standardised template for the delivery of a healthacre input to children in special schools is apparent. This study sought to explore through the use of an indepth needs assessment exercise and focus group interviews, what the most appropriate healthcare roelewas for delivering heathcare in a special school catering for children with a broad range of severe learning disabilities. While an overwhelming viewpoint of participants in focus gorups perceived that a nurse was the only suitable person to undertake the role, the evidence gathered promoted the research steering group to suggest to the contrary, i.e. that the role of a healthcare with a national vocational qualification (NVQ) level 3 in care was more the appropriate person to maximise both the role of the nurse and the quality of care provided to these children.

Area-efficient high-speed 3D DWT processor architecture

An area-efficient high-throughput architecture based on distributed arithmetic is proposed for 3D discrete wavelet transform (DWT). The 3D DWT processor was designed in VHDL and mapped to a Xilinx Virtex-E FPGA. The processor runs up to 85 MHz, which can process the five-level DWT analysis of a 128 x 128 x 128 fMRI volume image in 20 ms.

High-performance 3D median filter architecture for medical image despeckling

A high-sample rate 3D median filtering processor architecture is proposed, based on a novel 3D median filtering algorithm, that can reduce the computing complexity in comparison with the traditional bubble sorting algorithm. A 3 x 3 x 3 filter processor is implemented in VHDL, and the simulation verifies that the processor can process a 128 x 128 x 96 MRI image in 0.03 seconds while running at 50 MHz.

Low-power systolic array processor architecture for FSBM video motion estimation

A novel power-efficient systolic array architecture is proposed for full search block matching (FSBM) motion estimation, where the partial distortion elimination algorithm is used to dynamically switch off the computation of eliminated partial candidate blocks. The RTL-level simulation shows that the proposed architecture can reduce the power consumption of the computation part of the algorithm to about 60% of that of the conventional 2D systolic arrays.