Bit-Level systolic architectures for high performance IIR filtering

Several novel systolic architectures for implementing densely pipelined bit parallel IIR filter sections are presented. The fundamental problem of latency in the feedback loop is overcome by employing redundant arithmetic in combination with bit-level feedback, allowing a basic first-order section to achieve a wordlength-independent latency of only two clock cycles. This is extended to produce a building block from which higher order sections can be constructed. The architecture is then refined by combining the use of both conventional and redundant arithmetic, resulting in two new structures offering substantial hardware savings over the original design. In contrast to alternative techniques, bit-level pipelinability is achieved with no net cost in hardware. © 1989 Kluwer Academic Publishers.

Bit-level systolic architecture for very high performance IIR filters

A novel bit-level systolic array architecture for implementing bit-parallel IIR filter sections is presented. The authors have shown previously how the fundamental obstacle of pipeline latency in recursive structures can be overcome by the use of redundant arithmetic in combination with bit-level feedback. These ideas are extended by optimizing the degree of redundancy used in different parts of the circuit and combining redundant circuit techniques with those of conventional arithmetic. The resultant architecture offers significant improvements in hardware complexity and throughput rate.

SYSTOLIC IMPLEMENTATION OF THE WINOGRAD FOURIER TRANSFORM ALGORITHM.

A bit-level systolic array system is proposed for the Winograd Fourier transform algorithm. The design uses bit-serial arithmetic and, in common with other systolic arrays, features nearest neighbor interconnections, regularity, and high throughput. The short interconnections in this method contrast favorably with the long interconnections between butterflies required in the FFT. The structure is well suited to VLSI implementations. It is demonstrated how long transforms can be implemented with components designed to perform short-length transforms. These components build into longer transforms, preserving the regularity and structure of the short-length transform design.

Systematic methodology for the design of high performance recursive digital filters

A systematic design methodology is described for the rapid derivation of VLSI architectures for implementing high performance recursive digital filters, particularly ones based on most significant digit (msd) first arithmetic. The method has been derived by undertaking theoretical investigations of msd first multiply-accumulate algorithms and by deriving important relationships governing the dependencies between circuit latency, levels of pipe-lining and the range and number representations of filter operands. The techniques described are general and can be applied to both bit parallel and bit serial circuits, including those based on on-line arithmetic. The method is illustrated by applying it to the design of a number of highly pipelined bit parallel IIR and wave digital filter circuits. It is shown that established architectures, which were previously designed using heuristic techniques, can be derived directly from the equations described.

Fast VLSI algorithms for division and square root

Real time digital signal processing demands high performance implementations of division and square root. This can only be achieved by the design of fast and efficient arithmetic algorithms which address practical VLSI architectural design issues. In this paper, new algorithms for division and square root are described. The new schemes are based on pre-scaling the operands and modifying the classical SRT method such that the result digits and the remainders are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance exceeds that of the SRT methods. The hardware cost for higher radices is considerably more than that of the SRT methods but for many applications, this is not prohibitive. A system of equations is presented which enables both an analysis of the method for any radix and the parameters of implementations to be easily determined. This is illustrated for the case of radix 2 and radix 4. In addition, a highly regular array architecture combining the division and square root method is described. © 1994 Kluwer Academic Publishers.

Pipelined two-port adaptor for wave digital filtering

The application of fine-grain pipelining techniques in the design of high-performance wave digital filters (WDFs) is described. The problems of latency in feedback loops can be significantly reduced if computations are organized most significant, as opposed to least significant, bit first and if the results are fed back as soon as they are formed. The result is that chips can be designed which offer significantly higher sampling rates than otherwise can be obtained using conventional methods. How these concepts can be extended to the more challenging problem of WDFs is discussed. It is shown that significant increases in the sampling rate of bit-parallel circuits can be achieved using most significant bit first arithmetic.

Hardware elliptic curve cryptographic processor over GF(p)

A novel hardware architecture for elliptic curve cryptography (ECC) over GF(p) is introduced. This can perform the main prime field arithmetic functions needed in these cryptosystems including modular inversion and multiplication. This is based on a new unified modular inversion algorithm that offers considerable improvement over previous ECC techniques that use Fermat's Little Theorem for this operation. The processor described uses a full-word multiplier which requires much fewer clock cycles than previous methods, while still maintaining a competitive critical path delay. The benefits of the approach have been demonstrated by utilizing these techniques to create a field-programmable gate array (FPGA) design. This can perform a 256-bit prime field scalar point multiplication in 3.86 ms, the fastest FPGA time reported to date. The ECC architecture described can also perform four different types of modular inversion, making it suitable for use in many different ECC applications. © 2006 IEEE.

New algorithms and VLSI architectures for SRT division and square root

In real time digital signal processing, high performance modules for division and square root are essential if many powerful algorithms are to be implemented. In this paper, a new radix 2 algorithms for SRT division and square root are developed. For these new schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures to implement the new division and square root schemes are also presented.

Constant scale factor, on-line CORDIC algorithm in the circular coordinate system

Real time digital signal processing requires the development of high performance arithmetic algorithms suitable for VLSI design. In this paper, a new online, circular coordinate system CORDIC algorithm is described, which has a constant scale factor. This algorithm was developed using a new Angular Representation (AR) model A radix 2 version of the CORDIC algorithm is presented, along with an architecture suitable for VLSI implementation.

Optimized bit level architectures for IIR filtering

Optimized circuits for implementing high-performance bit-parallel IIR filters are presented. Circuits constructed mainly from simple carry save adders and based on most-significant-bit (MSB) first arithmetic are described. Two methods resulting in systems which are 100% efficient in that they are capable of sampling data every cycle are presented. In the first approach the basic circuit is modified so that the level of pipelining used is compatible with the small, but fixed, latency associated with the computation in question. This is achieved through insertion of pipeline delays (half latches) on every second row of cells. This produces an area-efficient solution in which the throughput rate is determined by a critical path of 76 gate delays. A second approach combines the MSB first arithmetic methods with the scattered look-ahead methods. Important design issues are addressed, including wordlength truncation, overflow detection, and saturation.

A longitudinal analysis of estimation, counting skills, and mathematical ability across the first school year

In response to claims that the quality (and in particular linearity) of children's mental representation of number acts as a constraint on number development, we carried out a longitudinal assessment of the relationships between number line estimation, counting, and mathematical abilities. Ninety-nine 5-year-olds were tested on 4 occasions at 3 monthly intervals. Correlations between the 3 types of ability were evident, but while the quality of children's estimations changed over time and performance on the mathematical tasks improved over the same period, changes in one were not associated with changes in the other. In contrast to the earlier claims that the linearity of number representation is potentially a unique contributor to children's mathematical development, the data suggest that this variable is not significantly privileged in its impact over and above simple procedural number skills. We propose that both early arithmetic success and estimating skill are bound closely to developments in counting ability.

Teenagers born at extremely low birth weight

Adolescence constitutes a major transition for extremely low birth weight (ELBW) teenagers. Recent studies of ELBW teenagers born in the 1980s have provided information about the growth and developmental characteristics of these individuals in adolescence and in early adulthood. ELBW teenagers are shorter and lighter than their full-term peers, and have a smaller head circumference. Cognitive and academic vulnerabilities documented during the school years, particularly difficulties with nonverbal intelligence and arithmetic, persist into late adolescence. Many ELBW children struggle in school and have lower academic achievement levels. The self-concept of ELBW teenagers is generally similar to that of their full-term peers, but their parents perceive them to be more vulnerable over a wide range of behavioural and psychosocial dimensions, particularly depression and attention. ELBW teenagers perceive themselves as needing more assistance in job seeking than do their peers. Physical activity levels and fitness in late adolescence are significantly lower in ELBW teenagers than in their full-term peers, constituting a potential additional health hazard in later life. The outcomes of ELBW teenagers are significantly influenced by socioeconomic, family and parenting factors.

Developmental coordination disorder in extremely low birth weight children at nine years

Developmental coordination disorder (DCD) is defined as an impairment in the development of motor coordination that interferes with academic achievement or activities of daily living (DSM-IV). DCD has been reported to affect 5% to 9% of children in the normal population. This study describes the prevalence of DCD in a cohort of extremely low birth weight children (ELBW, <or = l800 g) at 8.9 years of age, from which were excluded children with major impairments. Seventy-three children were included in the study group, along with 18 term-born, socially matched controls. Of the 73 ELBW children, 37 (51%) were classified as having DCD. ELBW children with DCD also had significantly lower Performance IQ (PIQ) scores and were more likely (43%) to have a learning difficulty in arithmetic than ELBW children who did not have DCD. This study found that DCD is a common problem in school-aged ELBW children.

A Tunable Encryption Scheme and Analysis of Fast Selective Encryption for CAVLC and CABAC in H.264/AVC

Recently, two fast selective encryption methods for context-adaptive variable length coding and context-adaptive binary arithmetic coding in H.264/AVC were proposed by Shahid et al. In this paper, it was demonstrated that these two methods are not as efficient as only encrypting the sign bits of nonzero coefficients. Experimental results showed that without encrypting the sign bits of nonzero coefficients, these two methods can not provide a perceptual scrambling effect. If a much stronger scrambling effect is required, intra prediction modes, and the sign bits of motion vectors can be encrypted together with the sign bits of nonzero coefficients. For practical applications, the required encryption scheme should be customized according to a user's specified requirement on the perceptual scrambling effect and the computational cost. Thus, a tunable encryption scheme combining these three methods is proposed for H.264/AVC. To simplify its implementation and reduce the computational cost, a simple control mechanism is proposed to adjust the control factors. Experimental results show that this scheme can provide different scrambling levels by adjusting three control factors with no or very little impact on the compression performance. The proposed scheme can run in real-time and its computational cost is minimal. The security of the proposed scheme is also discussed. It is secure against the replacement attack when all three control factors are set to one.

An optimisation of Gaussian mixture models for integer processing units

This paper investigates sub-integer implementations of the adaptive Gaussian mixture model (GMM) for background/foreground segmentation to allow the deployment of the method on low cost/low power processors that lack Floating Point Unit (FPU). We propose two novel integer computer arithmetic techniques to update Gaussian parameters. Specifically, the mean value and the variance of each Gaussian are updated by a redefined and generalised "round'' operation that emulates the original updating rules for a large set of learning rates. Weights are represented by counters that are updated following stochastic rules to allow a wider range of learning rates and the weight trend is approximated by a line or a staircase. We demonstrate that the memory footprint and computational cost of GMM are significantly reduced, without significantly affecting the performance of background/foreground segmentation.