On-off based charging strategies for EVs connected to a Low Voltage distributon network

The development of appropriate Electric Vehicle (EV) charging strategies has been identified as an effective way to accommodate an increasing number of EVs on Low Voltage (LV) distribution networks. Most research studies to date assume that future charging facilities will be capable of regulating charge rates continuously, while very few papers consider the more realistic situation of EV chargers that support only on-off charging functionality. In this work, a distributed charging algorithm applicable to on-off based charging systems is presented. Then, a modified version of the algorithm is proposed to incorporate real power system constraints. Both algorithms are compared with uncontrolled and centralized charging strategies from the perspective of both utilities and customers. © 2013 IEEE.

Feasibility of online collaborative voltage stability control of power systems

This paper presents the results of feasibility study of a novel concept of power system on-line collaborative voltage stability control. The proposal of the on-line collaboration between power system controllers is to enhance their overall performance and efficiency to cope with the increasing operational uncertainty of modern power systems. In the paper, the framework of proposed on-line collaborative voltage stability control is firstly presented, which is based on the deployment of multi-agent systems and real-time communication for on-line collaborative control. Then two of the most important issues in implementing the proposed on-line collaborative voltage stability control are addressed: (1) Error-tolerant communication protocol for fast information exchange among multiple intelligent agents; (2) Deployment of multi-agent systems by using graph theory to implement power system post-emergency control. In the paper, the proposed on-line collaborative voltage stability control is tested in the example 10-machine 39-node New England power system. Results of feasibility study from simulation are given considering the low-probability power system cascading faults.

The role of the relative voltage and phase for frequency coupling in a dual-frequency capacitively coupled plasma

Frequency coupling in multifrequency discharges is a complex nonlinear interaction of the different frequency components. An alpha-mode low pressure rf capacitively coupled plasma operated simultaneously with two frequencies is investigated and the coupling of the two frequencies is observed to greatly influence the excitation and ionization within the discharge. Through this, plasma production and sustainment are dictated by the corresponding electron dynamics and can be manipulated through the dual-frequency sheath. These mechanisms are influenced by the relative voltage and also the relative phase of the two frequencies.

High-density and low electron temperature direct current reflex plasma source

A new type of direct current, high-density, and low electron temperature reflex plasma source, obtained as a hybrid between a modified hollow-cathode discharge and a Penning ionization gauge discharge is presented. The plasma source was tested in argon, nitrogen, and oxygen over a range pressure of 1.0-10(-3) mbar, discharge currents 20-200 mA, and magnetic field 0-120 Gauss. Both external parameters, such as breakdown potential and the discharge voltage-current characteristic, and its internal parameters, like the electron energy distribution function, electron and ion densities, and electron temperature, were measured. Due to the enhanced hollow-cathode effect by the magnetic trapping of electrons, the density of the bulk plasma is as high as 10(18) m(-3), and the electron temperature is as low as a few tenths of electron volts. The plasma density scales with the dissipated power. Another important feature of this reflex plasma source is its high degree of uniformity, while the discharge bulk region is free of an electric field. (C) 2004 American Institute of Physics.

The Langmuir probe as a diagnostic of the electron component within low temperature laser ablated plasma plumes

A Langmuir probe has been used as a diagnostic of the temporally evolving electron component within a laser ablated Cu plasma expanding into vacuum, for an incident laser power density on target similar to that used for the pulsed laser deposition of thin films. Electron temperature data were obtained from the retarding region of the probe current/voltage (I/V) characteristic, which was also used to calculate an associated electron number density. Additionally, electron number density data were obtained from the saturation electron current region of the probe (I/V) characteristic. Electron number density data, extracted by the two different techniques, were observed to show the same temporal form, with measured absolute values agreeing to within a factor of 2. The Langmuir probe, in the saturation current region, has been shown for the first time to be a convenient diagnostic of the electron component within relatively low temperature laser ablated plasma plumes. (C) 1999 American Institute of Physics. [S0034-6748(99)01503-8].

TEMPORALLY AND SPATIALLY-RESOLVED PLASMA PARAMETERS AND EEDF MEASUREMENTS IN A LOW-FREQUENCY DISCHARGE

A time-resolved Langmuir probe technique is used to measure the dependence of the electron density, electron temperature, plasma potential and electron energy distribution function (EEDF) on the phase of the driving voltage in a RF driven parallel plate discharge. The measurements were made in a low-frequency (100-500 kHz), symmetrically driven, radio frequency discharge operating in H-2, D-2 and Ar at gas pressures of a few hundred millitorr. The EEDFs could not be represented by a single Maxwellian distribution and resembled the time averaged EEDFs reported in 13.56 MHz discharges. The measured parameters showed structure in their spatial and temporal dependence, generally consistent with a simple oscillating sheath model. Electron temperatures of less than 0.1 eV were measured during the phase of the RF cycle when both electrodes are negative with respect to the plasma.

A 76-84 GHz SiGe power amplifier array employing low-loss four-way differential combining transformer

This paper presents holistic design of a novel four-way differential power-combining transformer for use in millimeter-wave power-amplifier (PA). The combiner with an inner radius of 25 µm exhibits a record low insertion loss of 1.25 dB at 83.5 GHz. It is designed to simultaneously act as a balanced-to-unbalanced converter, removing the need for additional BALUNs typically required in differential circuits. A complete circuit comprised of a power splitter, two-stage differential cascode PA array, a power combiner as well as input and output matching elements was designed and realized in SiGe technology with f/f 170/250 GHz. Measured small-signal gain of at least 16.8 dB was obtained from 76.4 to 85.3 GHz with a peak 19.5 dB at 83 GHz. The prototype delivered 12.5 dBm output referred 1 dB compression point and 14 dBm saturated output power when operated from a 3.2 V dc supply voltage at 78 GHz.

Distribution Network Voltage Support Using Sensitivity-based Dispatch of Distributed Generation

This paper is concerned with the voltage and reactive power issues surrounding the connection of Distributed Generation (DG) on the low-voltage (LV) distribution network. The presented system-wide voltage control algorithm consists of three stages. Firstly available reactive power reserves are utilized. Then, if required, DG active power output is curtailed. Finally, curtailment of non-critical site demand is considered. The control methodology is tested on a variant of the 13-bus IEEE Node Radial Distribution Test Feeder. The presented control algorithm demonstrated that the distribution system operator (DSO) can maintain voltage levels within a desired statutory range by dispatching reactive power from DG or network devices. The practical application of the control strategy is discussed.

Design methodology for low power and arametric robustness through output-quality modulation:Application to color-interpolation filtering

Power dissipation and robustness to process variation have conflicting design requirements. Scaling of voltage is associated with larger variations, while Vdd upscaling or transistor upsizing for parametric-delay variation tolerance can be detrimental for power dissipation. However, for a class of signal-processing systems, effective tradeoff can be achieved between Vdd scaling, variation tolerance, and output quality. In this paper, we develop a novel low-power variation-tolerant algorithm/architecture for color interpolation that allows a graceful degradation in the peak-signal-to-noise ratio (PSNR) under aggressive voltage scaling as well as extreme process variations. This feature is achieved by exploiting the fact that all computations used in interpolating the pixel values do not equally contribute to PSNR improvement. In the presence of Vdd scaling and process variations, the architecture ensures that only the less important computations are affected by delay failures. We also propose a different sliding-window size than the conventional one to improve interpolation performance by a factor of two with negligible overhead. Simulation results show that, even at a scaled voltage of 77% of nominal value, our design provides reasonable image PSNR with 40% power savings. © 2006 IEEE.

Process variation tolerant low power DCT architecture

2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive voltage scaling by exploiting the fact that not all intermediate computations are equally important in a DCT system to obtain "good" image quality with Peak Signal to Noise Ratio(PSNR) > 30 dB. This observation has led us to propose a DCT architecture where the signal paths that are less contributive to PSNR improvement are designed to be longer than the paths that are more contributive to PSNR improvement. It should also be noted that robustness with respect to parameter variations and low power operation typically impose contradictory requirements in terms of architecture design. However, the proposed architecture lends itself to aggressive voltage scaling for low-power dissipation even under process parameter variations. Under a scaled supply voltage and/or variations in process parameters, any possible delay errors would only appear from the long paths that are less contributive towards PSNR improvement, providing large improvement in power dissipation with small PSNR degradation. Results show that even under large process variation and supply voltage scaling (0.8V), there is a gradual degradation of image quality with considerable power savings (62.8%) for the proposed architecture when compared to existing implementations in 70 nm process technology.

Low-Power Process-Variation Tolerant Arithmetic Units Using Input-Based Elastic Clocking

In this paper we propose a design methodology for low-power high-performance, process-variation tolerant architecture for arithmetic units. The novelty of our approach lies in the fact that possible delay failures due to process variations and/or voltage scaling are predicted in advance and addressed by employing an elastic clocking technique. The prediction mechanism exploits the dependence of delay of arithmetic units upon input data patterns and identifies specific inputs that activate the critical path. Under iso-yield conditions, the proposed design operates at a lower scaled down Vdd without any performance degradation, while it ensures a superlative yield under a design style employing nominal supply and transistor threshold voltage. Simulation results show power savings of upto 29%, energy per computation savings of upto 25.5% and yield enhancement of upto 11.1% compared to the conventional adders and multipliers implemented in the 70nm BPTM technology. We incorporated the proposed modules in the execution unit of a five stage DLX pipeline to measure performance using SPEC2000 benchmarks [9]. Maximum area and throughput penalty obtained were 10% and 3% respectively.

Significance Driven Computation: A Voltage-Scalable, Variation-Aware, Quality-Tuning Motion Estimator

In this paper we present a design methodology for algorithm/architecture co-design of a voltage-scalable, process variation aware motion estimator based on significance driven computation. The fundamental premise of our approach lies in the fact that all computations are not equally significant in shaping the output response of video systems. We use a statistical technique to intelligently identify these significant/not-so-significant computations at the algorithmic level and subsequently change the underlying architecture such that the significant computations are computed in an error free manner under voltage over-scaling. Furthermore, our design includes an adaptive quality compensation (AQC) block which "tunes" the algorithm and architecture depending on the magnitude of voltage over-scaling and severity of process variations. Simulation results show average power savings of similar to 33% for the proposed architecture when compared to conventional implementation in the 90 nm CMOS technology. The maximum output quality loss in terms of Peak Signal to Noise Ratio (PSNR) was similar to 1 dB without incurring any throughput penalty.

Multi-Level Wordline Driver for Low Power SRAMs in Nano-Scale CMOS Technology

In this paper, a multi-level wordline driver scheme is presented to improve SRAM read and write stability while lowering power consumption during hold operation. The proposed circuit applies a shaped wordline voltage pulse during read mode and a boosted wordline pulse during write mode. During read, the applied shaped pulse is tuned at nominal voltage for short period of time, whereas for the remaining access time, the wordline voltage is reduced to a lower level. This pulse results in improved read noise margin without any degradation in access time which is explained by examining the dynamic and nonlinear behavior of the SRAM cell. Furthermore, during hold mode, the wordline voltage starts from a negative value and reaches zero voltage, resulting in a lower leakage current compared to conventional SRAM. Our simulations using TSMC 65nm process show that the proposed wordline driver results in 2X improvement in static read noise margin while the write margin is improved by 3X. In addition, the total leakage of the proposed SRAM is reduced by 10% while the total power is improved by 12% in the worst case scenario of a single SRAM cell. The total area penalty is 10% for a 128Kb standard SRAM array.

Containing the Nanometer "Pandora-Box": Cross-Layer Design Techniques for Variation Aware Low Power Systems

The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling-parameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of today's systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs ( logic, memory, mixed-signal) that are included in today's complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems.

Logic and Memory Design Based on Unequal Error Protection for Voltage-scalable, Robust and Adaptive DSP Systems

In this paper, we propose a system level design approach considering voltage over-scaling (VOS) that achieves error resiliency using unequal error protection of different computation elements, while incurring minor quality degradation. Depending on user specifications and severity of process variations/channel noise, the degree of VOS in each block of the system is adaptively tuned to ensure minimum system power while providing "just-the-right" amount of quality and robustness. This is achieved, by taking into consideration block level interactions and ensuring that under any change of operating conditions, only the "less-crucial" computations, that contribute less to block/system output quality, are affected. The proposed approach applies unequal error protection to various blocks of a system-logic and memory-and spans multiple layers of design hierarchy-algorithm, architecture and circuit. The design methodology when applied to a multimedia subsystem shows large power benefits ( up to 69% improvement in power consumption) at reasonable image quality while tolerating errors introduced due to VOS, process variations, and channel noise.