Improving f(MAX)/f(T) ratio in FinFETs using source/drain extension region engineering

A design methodology to optimise the ratio of maximum oscillation frequency to cutoff frequency, f(MAX)/f(T), in 60 nm FinFETs is presented. Results show that 25 to 60% improvement in f(MAX)/f(T) at drain currents of 20-300 mu A/mu m can be achieved in a non-overlap gate-source/drain architecture. The reported work provides new insights into the design and optimisation of nanoscale FinFETs for RF applications.

6-T SRAM cell design with nanoscale double-gate SOI MOSFETs: impact of source/drain engineering and circuit topology

The impact of source/drain engineering on the performance of a six-transistor (6-T) static random access memory (SRAM) cell, based on 22 nm double-gate (DG) SOI MOSFETs, has been analyzed using mixed-mode simulation, for three different circuit topologies for low voltage operation. The trade-offs associated with the various conflicting requirements relating to read/write/standby operations have been evaluated comprehensively in terms of eight performance metrics, namely retention noise margin, static noise margin, static voltage/current noise margin, write-ability current, write trip voltage/current and leakage current. Optimal design parameters with gate-underlap architecture have been identified to enhance the overall SRAM performance, and the influence of parasitic source/drain resistance and supply voltage scaling has been investigated. A gate-underlap device designed with a spacer-to-straggle (s/sigma) ratio in the range 2-3 yields improved SRAM performance metrics, regardless of circuit topology. An optimal two word-line double-gate SOI 6-T SRAM cell design exhibits a high SNM similar to 162 mV, I-wr similar to 35 mu A and low I-leak similar to 70 pA at V-DD = 0.6 V, while maintaining SNM similar to 30% V-DD over the supply voltage (V-DD) range of 0.4-0.9 V.

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A(vo)) and cut-off frequency (f(T)) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 mu A/mu m, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SIDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g(m)), transconductance-to-current ratio (g(m)/I-ds), Early voltage (V-EA), output conductance (g(ds)) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs. (C) 2007 Elsevier B.V. All rights reserved.

Source/drain extension region engineering in FinFETs for low-voltage analog applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A(vo)) and cutoff frequency (f(T)) of 25-nm gate-length FinFETs operated at low drain-current (I-ds = 10 mu A/mu m). SDE region optimization in 25-nm FinFETs results in exceptionally high values of Avo (similar to 45 dB) and f(T) (similar to 70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs.

Engineering source/drain extension regions in nanoscale double gate (DG) SOI MOSFETs: Analytical model and design considerations

In this paper, we propose for the first time, an analytical model for short channel effects in nanoscale source/drain extension region engineered double gate (DG) SOI MOSFETs. The impact of (i) lateral source/drain doping gradient (d), (ii) spacer width (s), (iii) spacer to doping gradient ratio (s/d) and (iv) silicon film thickness (T-si), on short channel effects - threshold voltage (V-th) and subthreshold slope (S), on-current (I-on), off-current (I-on) and I-on/I-off is extensively analysed by using the analytical model and 2D device simulations. The results of the analytical model confirm well with simulated data over the entire range of spacer widths, doping gradients and effective channel lengths. Results show that lateral source/drain doping gradient along with spacer width can not only effectively control short channel effects, thus presenting low off-current, but can also be optimised to achieve high values of on-currents. The present work provides valuable design insights in the performance of nanoscale DG Sol devices with optimal source/drain engineering and serves as a tool to optimise important device and technological parameters for 65 nm technology node and below. (c) 2006 Elsevier Ltd. All rights reserved.

CO dissociation and O removal on Co(0001): a density functional theory study

CO dissociation and O removal (water formation) are two important processes in the Fischer-Tropsch synthesis. In this study, both processes are studied on the flat and stepped Co(0 0 0 1) using density functional theory. It is found that (i) it is difficult for CO to dissociate on the flat Co(0 0 0 1) due to the high barrier of 1.04 eV relative to the CO molecule in the gas phase; (ii) the stepped Co(0 0 0 1) is much more favoured for CO dissociation; (iii) the first step in water formation, O + H --> OH, is unlikely to occur on the flat Co(0 0 0 1) due to the high barrier of 1.72 eV, however, this reaction can become feasible on steps where the barrier is reduced to 0.73 eV; and (iv) the barrier in the second step, OH + H --> H2O, on steps is higher than that on the flat surface. (C) 2004 Elsevier B.V. All rights reserved.

The removal of dyes from textile wastewater: a study of the physical characteristics and adsorption mechanisms of diatomaceous earth

The feasibility of using diatomite for the removal of the problematic reactive dyes as well as basic dyes from textile wastewater was investigated. Methylene blue, Cibacron reactive black and reactive yellow dyes were considered. Physical characteristics of diatomite such as pH(solution), pH(ZPC), surface area, Fourier transform infrared, and scanning electron microscopy were investigated. The surface area of diatomite was found to be 27.80 m(2) g(-1) and the pH(ZPC) occurred around pH of 5.4. The results indicated that the surface charge of diatomite decreased as the pH of the solution increased with the maximum methylene blue removal from aqueous solution occurring at basic pH of around (1011). Adsorption isotherms of diatomite with methylene blue, hydrolysed reactive black and yellow dyes were constructed at different pH values, initial dye concentrations and particle sizes. The experimental results were fitted to the Langmuir, Freundlich, and Henry models. The study indicated that electrostatic interactions play an important role in the adsorption of dyes onto diatomite. A model of the adsorption mechanism of methylene blue onto diatomite is proposed. (C) 2003 Elsevier Ltd. All rights reserved.

Objective assessment of cardiopulmonary resuscitation skills of 10-11 year-old schoolchildren using two different external chest compression to ventilation ratios

Study which shows that 10-11 yr olds are capable of effective CPR after a single 2 hour training session using the ABC for Life programme. However they perfrom more effective CPR when using a ratio of 15:2 rather than 30:2 chest compressions : ventilations