An efficient neural network approach for nanoscale FinFET modelling and circuit simulation

The present paper demonstrates the suitability of artificial neural network (ANN) for modelling of a FinFET in nano-circuit simulation. The FinFET used in this work is designed using careful engineering of source-drain extension, which simultaneously improves maximum frequency of oscillation f(max) because of lower gate to drain capacitance, and intrinsic gain A(V0) = g(m)/g(ds), due to lower output conductance g(ds). The framework for the ANN-based FinFET model is a common source equivalent circuit, where the dependence of intrinsic capacitances, resistances and dc drain current I-d on drain-source V-ds and gate-source V-gs is derived by a simple two-layered neural network architecture. All extrinsic components of the FinFET model are treated as bias independent. The model was implemented in a circuit simulator and verified by its ability to generate accurate response to excitations not used during training. The model was used to design a low-noise amplifier. At low power (J(ds) similar to 10 mu A/mu m) improvement was observed in both third-order-intercept IIP3 (similar to 10 dBm) and intrinsic gain A(V0) (similar to 20 dB), compared to a comparable bulk MOSFET with similar effective channel length. This is attributed to higher ratio of first-order to third-order derivative of I-d with respect to gate voltage and lower g(ds), in FinFET compared to bulk MOSFET. Copyright (C) 2009 John Wiley & Sons, Ltd.

Millimeter-wave printed circuit board characterization using substrate integrated waveguide resonators

This paper proposes a substrate integrated waveguide
(SIW) cavity-based method that is compliant with
ground-signal–ground (GSG) probing technology for dielectric
characterization of printed circuit board materials at millimeter
wavelengths. This paper presents the theory necessary to retrieve
dielectric parameters from the resonant characteristics of SIW
cavities with particular attention placed on the coupling scheme
and means for obtaining the unloaded resonant frequency. Different
sets of samples are designed and measured to address the
influence of the manufacturing process on the method. Material
parameters are extracted at - and -band from measured data
with the effect of surface roughness of the circuit metallization
taken into account.

Electronic Circuit Packages

This invention relates to electronic circuit packages designed to hold high frequency circuits operating particularly, but not exclusively, in the microwave, millimeter wave, and sub-millimeter wave bands. The invention provides a package incorporating a cavity in a material for containment of the circuits, wherein the package further incorporates at least one conductive surface mounted on an inner surface extending into the cavity, the conductivity thereof being adapted to be at least partially absorbent to electromagnetic radiation. The conductive surface according to the present invention will tend to attenuate electromagnetic radiation present within the cavity, and so help to prevent undesired coupling from one point to another within the cavity. The conductivity of the conductive material is preferably arranged to match the impedance of the radiation mode estimated or computed to be present within the cavity.

Implementation of a network flow lookup circuit for next-generation packet classifiers

This paper presents a lookup circuit with advanced memory techniques and algorithms that examines network packet headers at high throughput rates. Hardware solutions and test scenarios are introduced to evaluate the proposed approach. The experimental results show that the proposed lookup circuit is able to achieve at least 39 million packet header lookups per second, which facilitates the application of next-generation stateful packet classifications at beyond 20Gbps internet traffic throughput rates.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

High performance IP lookup circuit using DDR SDRAM

DDR-SDRAM based data lookup techniques are evolving into a core technology for packet lookup applications for data network, benefitting from the features of high density, high bandwidth and low price of DDR memory products in the market. Our proposed DDR-SDRAM based lookup circuit is capable of achieving IP header lookup for network line-rates of up to 10Gbps, providing a solution on high-performance and economic packet header inspections. ©2008 IEEE.

Design and analysis of matching circuit architectures for a closest match lookup

This paper investigates the implementation of a number of circuits used to perform a high speed closest value match lookup. The design is targeted particularly for use in a search trie, as used in various networking lookup applications, but can be applied to many other areas where such a match is required. A range of different designs have been considered and implemented on FPGA. A detailed description of the architectures investigated is followed by an analysis of the synthesis results. © 2006 IEEE.