Using signed digit arithmetic for low-power multiplication

Hardware implementations of arithmetic operators using signed digit arithmetic have lost some of their earlier popularity. However, SD is revisited and used to realise an efficient radix-16 generic multiplier, which has particular potential for low-power implementation. The SD multiplier algorithm reduces the number of partial products to as much as 1/4, and in initial tests reduces the estimated power consumption to only about 50% of that of the Booth multiplier. It is different from other previous high-radix methods in that it employs a novel method to generate its partial products with zero arithmetic logic.

2-D R-matrix propagation: A large scale electron scattering simulation dominated by the multiplication of dynamically changing matrices

We examine the computational aspects of propagating a global R-matrix, R, across sub-regions in a 2-D plane. This problem originates in the large scale simulation of electron collisions with atoms and ions at intermediate energies. The propagation is dominated by matrix multiplications which are complicated because of the dynamic nature of R, which changes the designations of its rows and columns and grows in size as the propagation proceeds. The use of PBLAS to solve this problem on distributed memory HPC machines is the main focus of the paper.

BIT-LEVEL SYSTOLIC ARRAY CIRCUIT FOR MATRIX VECTOR MULTIPLICATION.

A bit-level systolic array for computing matrix x vector products is described. The operation is carried out on bit parallel input data words and the basic circuit takes the form of a 1-bit slice. Several bit-slice components must be connected together to form the final result, and authors outline two different ways in which this can be done. The basic array also has considerable potential as a stand-alone device, and its use in computing the Walsh-Hadamard transform and discrete Fourier transform operations is briefly discussed.

A VLSI architecture for multiplication, division and square root

A high-performance VLSI architecture to perform combined multiply-accumulate, divide, and square root operations is proposed. The circuit is highly regular, requires only minimal control, and can be reconfigured for every cycle. The execution time for each operation is the same. The combination of redundancy and pipelining results in a throughput independent of the wordsize of the array. With current CMOS technology, throughput rates in excess of 80 million operations per second are achievable.

Multiplication of microbes below 0.690 water activity: implications for terrestrial and extraterrestrial life

Since a key requirement of known life forms is available water (water activity; aw), recent searches for signatures of past life in terrestrial and extraterrestrial environments have targeted places known to have contained significant quantities of biologically available water. However, early life on Earth inhabited high-salt environments, suggesting an ability to withstand low water-activity. The lower limit of water activity that enables cell division appears to be ∼ 0.605 which, until now, was only known to be exhibited by a single eukaryote, the sugar-tolerant, fungal xerophile Xeromyces bisporus. The first forms of life on Earth were, though, prokaryotic. Recent evidence now indicates that some halophilic Archaea and Bacteria have water-activity limits more or less equal to those of X. bisporus. We discuss water activity in relation to the limits of Earth's present-day biosphere; the possibility of microbial multiplication by utilizing water from thin, aqueous films or non-liquid sources; whether prokaryotes were the first organisms able to multiply close to the 0.605-aw limit; and whether extraterrestrial aqueous milieux of ≥ 0.605 aw can resemble fertile microbial habitats found on Earth.

Accelerating integer-based fully homomorphic encryption using Comba multiplication

Fully Homomorphic Encryption (FHE) is a recently developed cryptographic technique which allows computations on encrypted data. There are many interesting applications for this encryption method, especially within cloud computing. However, the computational complexity is such that it is not yet practical for real-time applications. This work proposes optimised hardware architectures of the encryption step of an integer-based FHE scheme with the aim of improving its practicality. A low-area design and a high-speed parallel design are proposed and implemented on a Xilinx Virtex-7 FPGA, targeting the available DSP slices, which offer high-speed multiplication and accumulation. Both use the Comba multiplication scheduling method to manage the large multiplications required with uneven sized multiplicands and to minimise the number of read and write operations to RAM. Results show that speed up factors of 3.6 and 10.4 can be achieved for the encryption step with medium-sized security parameters for the low-area and parallel designs respectively, compared to the benchmark software implementation on an Intel Core2 Duo E8400 platform running at 3 GHz.