8 resultados para tri-gate transistor structure

em Biblioteca Digital da Produção Intelectual da Universidade de São Paulo


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In this work we have studied the radiation effects on MOSFET electronic devices. The integrated circuits were exposed to 10 key X-ray radiation and 2.6 MeV energy proton beam. We have irradiated MOSFET devices with two different geometries: rectangular-gate transistor and circular-gate transistor. We have observed the cumulative dose provokes shifts on the threshold voltage and increases or decreases the transistor's off-state and leakage current. The position of the trapped charges in modern CMOS technology devices depends on radiation type, dose rate, total dose, applied bias and is a function of device geometry. We concluded the circular-gate transistor is more tolerant to radiation than the rectangular-gate transistor. (C) 2011 Elsevier B.V. All rights reserved.

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In this work, the impact of global and/or local strain engineering techniques on tri-gate p- and nMuGFETs performance is experimentally evaluated. Multiple gate structures were analyzed through basic and analog performance parameters for four different splits processed with different strain-engineering techniques (unstrained, uniaxial, biaxial and uniaxial+biaxial stress). While n-channel devices with narrow fins present a worse analog behavior, biaxial stress promotes the electron mobility for larger devices increasing the voltage gain. Besides the voltage gain, the transconductance, output conductance and Early Voltage are also evaluated. Although pMuGFETs are less affected by the strain engineering, they present better analog behavior for all studied devices.

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In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple-gate FinFETs. The drain current, transconductance, resistance, threshold voltage, subthreshold swing and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. Moreover, for the first time, the important figures of merit for the analog performance such as transconductance-over-drain current, output conductance. Early voltage and intrinsic voltage gain will be studied experimentally and through three-dimensional (3-D) numerical simulations for different channel doping concentrations in triple-gate DTMOS FinFETs. The results indicate that the DTMOS FinFETs always yield superior characteristic; and larger transistor efficiency. In addition, DTMOS devices with a high channel doping concentration exhibit much better analog performance compared to the normal operation mode, which is desirable for high performance low-power/low-voltage applications. (C) 2011 Elsevier Ltd. All rights reserved.

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Vanadium/titanium mixed oxide films were produced using the sol-gel route. The structural investigation revealed that increased TiO2 molar ratio in the mixed oxide disturbs the V2O5 crystalline structure and makes it amorphous. This blocks the TiO2 phase transformation, so TiO2 stabilizes in the anatase phase. In addition the surface of the sample always presents larger amounts of TiO2 than expected, revealing a concentration gradient along the growth direction. For increased TiO2 molar ratios the roughness of the surface is reduced. Ion sensors were fabricated using the extended gate field effect transistor configuration. The obtained sensitivities varied in the range of 58 mV/pH down to 15 mV/pH according to the composition and morphology of the surface of the samples. Low TiO2 amounts presented better sensing properties that might be related to the cracked and inhomogeneous surfaces. Rising the TiO2 quantity in the films produces homogeneous surfaces but diminishes their sensitivities. Thus, the present paper reveals that the compositional and structural aspects change the surface morphology and electrical properties accounting for the final ion sensing properties of the V2O5/TiO2 films. (C) 2012 The Electrochemical Society. [DOI: 10.1149/2.053206jes] All rights reserved.

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Triple-gate devices are considered a promising solution for sub-20 nm era. Strain engineering has also been recognized as an alternative due to the increase in the carriers mobility it propitiates. The simulation of strained devices has the major drawback of the stress non-uniformity, which cannot be easily considered in a device TCAD simulation without the coupled process simulation that is time consuming and cumbersome task. However, it is mandatory to have accurate device simulation, with good correlation with experimental results of strained devices, allowing for in-depth physical insight as well as prediction on the stress impact on the device electrical characteristics. This work proposes the use of an analytic function, based on the literature, to describe accurately the strain dependence on both channel length and fin width in order to simulate adequately strained triple-gate devices. The maximum transconductance and the threshold voltage are used as the key parameters to compare simulated and experimental data. The results show the agreement of the proposed analytic function with the experimental results. Also, an analysis on the threshold voltage variation is carried out, showing that the stress affects the dependence of the threshold voltage on the temperature. (C) 2011 Elsevier Ltd. All rights reserved.

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The layer-by-layer (LbL) technique combined with field-effect transistor (FET) based sensors has enabled the production of pH-sensitive platforms with potential application in biosensors. A variation of the FET architecture, so called separative extended gate FET (SEGFET) devices, are promise as an alternative to conventional ion sensitive FET (ISFET). SEGFET configuration exhibits the advantage of combining the field-effect concept with organic and inorganic materials directly adsorbed on the extended gate, allowing the test of new pH-sensitive materials in a simple and low cost way. In this communication, poly(propylene imine) dendrimer (PPI) and TiO2 nanoparticles (TiO2-np) were assembled onto gold-covered substrates via layer-by-layer technique to produce a low cost SEGFET pH sensor. The sensor presented good pH sensitivity, ca. 57 mV pH(-1), showing that our strategy has potential advantages to fabricate low cost pH-sensing membranes. (C) 2012 Elsevier B.V. All rights reserved.

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The floating-body-RAM sense margin and retention-time dependence on the gate length is investigated in UTBOX devices using BJT programming combined with a positive back bias (so-called V th feedback). It is shown that the sense margin and the retention time can be kept constant versus the gate length by using a positive back bias. Nevertheless, below a critical L, there is no room for optimization, and the memory performances suddenly drop. The mechanism behind this degradation is attributed to GIDL current amplification by the lateral bipolar transistor with a narrow base. The gate length can be further scaled using underlap junctions.

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A model for computing the generation-recombination noise due to traps within the semiconductor film of fully depleted silicon-on-insulator MOSFET transistors is presented. Dependence of the corner frequency of the Lorentzian spectra on the gate voltage is addressed in this paper, which is different to the constant behavior expected for bulk transistors. The shift in the corner frequency makes the characterization process easier. It helps to identify the energy position, capture cross sections, and densities of the traps. This characterization task is carried out considering noise measurements of two different candidate structures for single-transistor dynamic random access memory devices.