Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop

In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area.

Integrated higher-order pulse-width modulation filter-transformer structure for single-phase static compensator

A power filter is necessary to connect the output of a power converter to the grid so as to reduce the harmonic distortion introduced in the line current and voltage by the power converter. Many a times, a transformer is also present before the point of common coupling. Magnetic components often constitute a significant part of the overall weight, size and cost of the grid interface scheme. So, a compact inexpensive design is desirable. A higher-order LCL-filter and a transformer are increasingly being considered for grid interconnection of the power converter. This study proposes a design method based on a three-winding transformer, that generates an integrated structure that behaves as an LCL-filter, with both the filter inductances and the transformer that are merged into a single electromagnetic component. The parameters of the transformer are derived analytically. It is shown that along with a filter capacitor, the transformer parameters provide the filtering action of an LCL-filter. A single-phase full-bridge power converter is operated as a static compensator for performance evaluation of the integrated filter transformer. A resonant integrator-based single-phase phase locked loop and stationary frame AC current controller are employed for grid frequency synchronisation and line current control, respectively.

Firing delay scheme for 3-Ï thyristor converters

A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

Simple equidistant firing delay scheme for 3-phi thyristor converters

A simple firing delay circuit for 3-φ fully controlled bridge using a phase locked loop is described. The circuit uses very few components and is an improved scheme over the existing methods. The use of this circuit in three-phase thyristor converters and 'circulating current free' mode dual converters is described.

Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance

In this brief, the substrate noise effects of a pulsed clocking scheme on the output spur level, the phase noise, and the peak-to-peak (Pk-Pk) deterministic period jitter of an integer-N charge-pump phase-locked loop (PLL) are demonstrated experimentally. The phenomenon of noise coupling to the PLL is also explained through experiments. The PLL output frequency is 500 MHz and it is implemented in the 0.13-mu m CMOS technology. Measurements show a reduction of 12.53 dB in the PLL output spur level at an offset of 5 MHz and a reduction of 107 ps in the Pk-Pk deterministic period jitter upon reducing the duty cycle of the signal injected into the substrate from 50% to 20%. The results of the analyses suggest that using a pulsed clocking scheme for digital systems in mixed-signal integration along with other isolation techniques helps reduce the substrate noise effects on sensitive analog/radio-frequency circuits.

Timing Recovery Algorithms and Architectures for 2-D Magnetic Recording Systems

We investigate the problem of timing recovery for 2-D magnetic recording (TDMR) channels. We develop a timing error model for TDMR channel considering the phase and frequency offsets with noise. We propose a 2-D data-aided phase-locked loop (PLL) architecture for tracking variations in the position and movement of the read head in the down-track and cross-track directions and analyze the convergence of the algorithm under non-separable timing errors. We further develop a 2-D interpolation-based timing recovery scheme that works in conjunction with the 2-D PLL. We quantify the efficiency of our proposed algorithms by simulations over a 2-D magnetic recording channel with timing errors.

Differential Multi-phase DLL for Reconfigurable Radio Frequency Synthesizer

A multi phase, delay-locked loop (DLL) based frequency synthesizer is designed for harmonic rejection mixing in reconfigurable radios. This frequency synthesizer uses a 1 GHz input reference frequency, and achieves <= 20ns settling time by utilizing a wide loop bandwidth. The circuit has been designed in 0.13-mu m CMOS technology. It is designed for a frequency range of 500 MHz to 3 GHz with stuck/harmonic lock removal assist. Index Terms-stuck lock, harmonic lock, delay-locked loops, multi phase, phase detector, frequency synthesis

Acquisition time improvement of PLLs using some aiding functions

Analytical studies are carried out to minimize acquisition time in phase-lock loop (PLL) applications using aiding functions. A second order aided PLL is realized with the help of the quasi-stationary approach to verify the acquisition behavior in the absence of noise. Time acquisition is measured both from the study of the LPF output transient and by employing a lock detecting and indicating circuit to crosscheck experimental and analytical results. A closed form solution is obtained for the evaluation of the time acquisition using different aiding functions. The aiding signal is simple and economical and can be used with state of the art hardware.

Developments in solid-state under-frequency relays

Simpler circuits for frequency-sensitive relays responding to change and rate of change of system frequency have been developed employing phase-locked loops. A new relay responding to time intergral of the fall in system frequency has also been developed and its performance has been compared with those responding to change and rate of change of system frequency. The relays have been tested and calibrated with the help of a specially designed calibration kit.

Optimal sparsifying bases for frequency-domain optical-coherence tomography

We address the reconstruction problem in frequency-domain optical-coherence tomography (FDOCT) from under-sampled measurements within the framework of compressed sensing (CS). Specifically, we propose optimal sparsifying bases for accurate reconstruction by analyzing the backscattered signal model. Although one might expect Fourier bases to be optimal for the FDOCT reconstruction problem, it turns out that the optimal sparsifying bases are windowed cosine functions where the window is the magnitude spectrum of the laser source. Further, the windowed cosine bases can be phase locked, which allows one to obtain higher accuracy in reconstruction. We present experimental validations on real data. The findings reported in this Letter are useful for optimal dictionary design within the framework of CS-FDOCT. (C) 2012 Optical Society of America

Analysis of Bandwidth-Unit-Vector-Distortion Tradeoff in PLL During Abnormal Grid Conditions

Phase-locked loops (PLLs) are necessary in applications which require grid synchronization. Presence of unbalance or harmonics in the grid voltage creates errors in the estimated frequency and angle of a PLL. The error in estimated angle has the effect of distorting the unit vectors generated by the PLL. In this paper, analytical expressions are derived which determine the error in the phase angle estimated by a PLL when there is unbalance and harmonics in the grid voltage. By using the derived expressions, the total harmonic distortion (THD) and the fundamental phase error of the unit vectors can be determined for a given PLL topology and a given level of unbalance and distortion in the grid voltage. The accuracy of the results obtained from the analytical expressions is validated with the simulation and experimental results for synchronous reference frame PLL (SRF-PLL). Based on these expressions, a new tuning method for the SRF-PLL is proposed which quantifies the tradeoff between the unit vector THD and the bandwidth of the SRF-PLL. Using this method, the exact value of the bandwidth of the SRF-PLL can be obtained for a given worst case grid voltage unbalance and distortion to have an acceptable level of unit vector THD. The tuning method for SRF-PLL is also validated experimentally.

A Novel Design Method for SOGI-PLL for Minimum Settling Time and Low Unit Vector Distortion

Phase-locked loops (PLLs) are necessary in grid connected systems to obtain information about the frequency, amplitude and phase of the grid voltage. In stationary reference frame control, the unit vectors of PLLs are used for reference generation. It is important that the PLL performance is not affected significantly when grid voltage undergoes amplitude and frequency variations. In this paper, a novel design for the popular single-phase PLL topology, namely the second-order generalized integrator (SOGI) based PLL is proposed which achieves minimum settling time during grid voltage amplitude and frequency variations. The proposed design achieves a settling time of less than 27.7 ms. This design also ensures that the unit vectors generated by this PLL have a steady state THD of less than 1% during frequency variations of the grid voltage. The design of the SOGI-PLL based on the theoretical analysis is validated by experimental results.

Response Dynamics of Recirculation Structures in Coaxial Nonpremixed Swirl-Stabilized Flames Subjected to Acoustic Forcing

This paper reports the time-mean and phase-locked response of nonreacting as well as reacting flow field in a coaxial swirling jet/flame (nonpremixed). Two distinct swirl intensities plus two different central pipe flow rates at each swirl setting are investigated. The maximum response is observed at the 105 Hz mode in the range of excitation frequencies (0-315 Hz). The flow/flame exhibited minimal response beyond 300 Hz. It is seen that the aspect ratio change of inner recirculation zone (IRZ) under nonreacting conditions (at responsive modes) manifests as a corresponding increase in the time-mean flame aspect ratio. This is corroborated by similar to 25% decrease in the IRZ transverse width in both flame and cold flow states. In addition, 105 Hz excited states are found to shed high energy regions (eddies) asymmetrically when compared to dormant 315 Hz pulsing frequency. The kinetic energy (KE) of the flow field is subsequently reduced due to acoustic excitation and a corresponding increase (similar to O (1)) in fluctuation intensity is witnessed. The lower swirl intensity case is found to be more responsive than the high swirl case as in the former flow state the resistance offered by IRZ to incoming acoustic perturbations is lower due to inherently low inertia. Next, the phase-locked analysis of flow and flame structure is employed to further investigate the phase dependence of flow/flame response. It is found that the asymmetric shifting of IRZ mainly results at 270 deg acoustic forcing. The 90 deg phase angle forcing is observed to convect the IRZ farther downstream in both swirl cases as compared to other phase angles. The present work aims primarily at providing a fluid dynamic view point to the observed nonpremixed flame response without considering the confinement effects.

Towards a temperature-guided molecular switch: an unusual reversible low-temperature polymorphic phase transition in a conformational locked environment

A conformationally locked tetraacetate undergoes, quite akin to a temperature-guided molecular switch, a reversible thermal switching between two polymorphic modifications; the room-temperature alpha-form converted at -4 degrees C to a low-temperature denser beta-form, which displayed an unusual kinetic stability till 67 degrees C and transformed back to the alpha-form beyond this temperature.

Construction of Stability Multipliers with Prescribed Phase Characteristics: an Improved Value for $\sigma

For a feedback system consisting of a transfer function $G(s)$ in the forward path and a time-varying gain $n(t)(0 \leqq n(t) \leqq k)$ in the feedback loop, a stability multiplier $Z(s)$ has been constructed (and used to prove stability) by Freedman [2] such that $Z(s)(G(s) + {1 / K})$ and $Z(s - \sigma )(0 < \sigma < \sigma _ * )$ are strictly positive real, where $\sigma _ * $ can be computed from a knowledge of the phase-angle characteristic of $G(i\omega ) + {1 / k}$ and the time-varying gain $n(t)$ is restricted by $\sigma _ * $ by means of an integral inequality. In this note it is shown that an improved value for $\sigma _ * $ is possible by making some modifications in his derivation. ©1973 Society for Industrial and Applied Mathematics.