Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop
Contribuinte(s) |
RG, Raghavendra Amrutur, Bharadwaj |
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Data(s) |
2007
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Resumo |
In this paper, two new dual-path based area efficient loop filtercircuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25 CSM analog process with 1.8V supply. The proposed circuits achievedup to 85% savings in capacitor area. Simulations showed goodmatch of the new circuits with the conventional circuit. Theproposed circuits are particularly useful in applications thatdemand low die area. |
Formato |
application/pdf |
Identificador |
http://eprints.iisc.ernet.in/22090/1/pdf.pdf Raghavendra, RG and Amrutur, Bharadwaj (2007) Area Efficient Loop Filter Design for Charge Pump Phase Locked Loop. In: Glsvlsi'07: proceedings of the 2007 acm great lakes symposium on vlsi, Mar,11-13, 2007, Sigda, pp. 148-151. |
Publicador |
Assoc computing machinery |
Relação |
http://eprints.iisc.ernet.in/22090/ |
Palavras-Chave | #Electrical Communication Engineering |
Tipo |
Conference Paper PeerReviewed |