55 resultados para Reconfigurable remote laboratories

em Indian Institute of Science - Bangalore - Índia


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We report the design and characterization of a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and noninverting) in its unmodified form. The test circuit comprises of digitally reconfigurable ring oscillator (RO). The gate under test is embedded in each stage of the ring oscillator. A system of linear equations is then formed with different configuration settings of the RO, relating the individual gate delay to the measured period of the RO, whose solution gives the delay of the individual gates. Experimental results from a test chip in 65-nm process node show the feasibility of measuring the delay of an individual inverter to within 1 ps accuracy. Delay measurements of different nominally identicall inverters in close physical proximity show variations of up to 28% indicating the large impact of local variations. As a demonstration of this technique, we have studied delay variation with poly-pitch, length of diffusion (LOD) and different orientations of layout in silicon. The proposed technique is quite suitable for early process characterization, monitoring mature process in manufacturing and correlating model-to-hardware.

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In this paper we develop compilation techniques for the realization of applications described in a High Level Language (HLL) onto a Runtime Reconfigurable Architecture. The compiler determines Hyper Operations (HyperOps) that are subgraphs of a data flow graph (of an application) and comprise elementary operations that have strong producer-consumer relationship. These HyperOps are hosted on computation structures that are provisioned on demand at runtime. We also report compiler optimizations that collectively reduce the overheads of data-driven computations in runtime reconfigurable architectures. On an average, HyperOps offer a 44% reduction in total execution time and a 18% reduction in management overheads as compared to using basic blocks as coarse grained operations. We show that HyperOps formed using our compiler are suitable to support data flow software pipelining.

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Emerging embedded applications are based on evolving standards (e.g., MPEG2/4, H.264/265, IEEE802.11a/b/g/n). Since most of these applications run on handheld devices, there is an increasing need for a single chip solution that can dynamically interoperate between different standards and their derivatives. In order to achieve high resource utilization and low power dissipation, we propose REDEFINE, a polymorphic ASIC in which specialized hardware units are replaced with basic hardware units that can create the same functionality by runtime re-composition. It is a ``future-proof'' custom hardware solution for multiple applications and their derivatives in a domain. In this article, we describe a compiler framework and supporting hardware comprising compute, storage, and communication resources. Applications described in high-level language (e.g., C) are compiled into application substructures. For each application substructure, a set of compute elements on the hardware are interconnected during runtime to form a pattern that closely matches the communication pattern of that particular application. The advantage is that the bounded CEs are neither processor cores nor logic elements as in FPGAs. Hence, REDEFINE offers the power and performance advantage of an ASIC and the hardware reconfigurability and programmability of that of an FPGA/instruction set processor. In addition, the hardware supports custom instruction pipelining. Existing instruction-set extensible processors determine a sequence of instructions that repeatedly occur within the application to create custom instructions at design time to speed up the execution of this sequence. We extend this scheme further, where a kernel is compiled into custom instructions that bear strong producer-consumer relationship (and not limited to frequently occurring sequences of instructions). Custom instructions, realized as hardware compositions effected at runtime, allow several instances of the same to be active in parallel. A key distinguishing factor in majority of the emerging embedded applications is stream processing. To reduce the overheads of data transfer between custom instructions, direct communication paths are employed among custom instructions. In this article, we present the overview of the hardware-aware compiler framework, which determines the NoC-aware schedule of transports of the data exchanged between the custom instructions on the interconnect. The results for the FFT kernel indicate a 25% reduction in the number of loads/stores, and throughput improves by log(n) for n-point FFT when compared to sequential implementation. Overall, REDEFINE offers flexibility and a runtime reconfigurability at the expense of 1.16x in power and 8x in area when compared to an ASIC. REDEFINE implementation consumes 0.1x the power of an FPGA implementation. In addition, the configuration overhead of the FPGA implementation is 1,000x more than that of REDEFINE.

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The knowledge of hydrological variables (e. g. soil moisture, evapotranspiration) are of pronounced importance in various applications including flood control, agricultural production and effective water resources management. These applications require the accurate prediction of hydrological variables spatially and temporally in watershed/basin. Though hydrological models can simulate these variables at desired resolution (spatial and temporal), often they are validated against the variables, which are either sparse in resolution (e. g. soil moisture) or averaged over large regions (e. g. runoff). A combination of the distributed hydrological model (DHM) and remote sensing (RS) has the potential to improve resolution. Data assimilation schemes can optimally combine DHM and RS. Retrieval of hydrological variables (e. g. soil moisture) from remote sensing and assimilating it in hydrological model requires validation of algorithms using field studies. Here we present a review of methodologies developed to assimilate RS in DHM and demonstrate the application for soil moisture in a small experimental watershed in south India.

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Extensive measurements of aerosol radiative and microphysical properties were made at an island location, Minicoy (8.3 degrees N, 73.04 degrees E) in the southern Arabian Sea. A large variability in aerosol characteristics associated with changes in air mass and precipitation characteristics was observed. Six distinct transport pathways were identified on the basis of cluster analysis. The Indo-Gangetic Plain, along with the northern Arabian Sea and west Asia (NWA), was identified to be the region having the highest potential for aerosol mass loading at the island. This estimate is based on the concentration weighted trajectory as well as cluster analysis. Dust transport from the NWA region was found to make a substantial contribution to the supermicron mass fraction. The black carbon mass mixing ratios observed were the lowest compared to previous measurements over this region. Consequently, the atmospheric radiative forcing efficiency was low and was in the range 10-28 W m(-2).

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In modern wireline and wireless communication systems, Viterbi decoder is one of the most compute intensive and essential elements. Each standard requires a different configuration of Viterbi decoder. Hence there is a need to design a flexible reconfigurable Viterbi decoder to support different configurations on a single platform. In this paper we present a reconfigurable Viterbi decoder which can be reconfigured for standards such as WCDMA, CDMA2000, IEEE 802.11, DAB, DVB, and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. Our design provides higher throughput and scalable power consumption in various configuration of the reconfigurable Viterbi decoder. The power and throughput can also be optimized for different standards.

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Owing to high evolutionary divergence, it is not always possible to identify distantly related protein domains by sequence search techniques. Intermediate sequences possess sequence features of more than one protein and facilitate detection of remotely related proteins. We have demonstrated recently the employment of Cascade PSI-BLAST where we perform PSI-BLAST for many 'generations', initiating searches from new homologues as well. Such a rigorous propagation through generations of PSI-BLAST employs effectively the role of intermediates in detecting distant similarities between proteins. This approach has been tested on a large number of folds and its performance in detecting superfamily level relationships is similar to 35% better than simple PSI-BLAST searches. We present a web server for this search method that permits users to perform Cascade PSI-BLAST searches against the Pfam, SCOP and SwissProt databases. The URL for this server is http://crick.mbu.iisc.ernet.in/similar to CASCADE/CascadeBlast.html.

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We propose an effective elastography technique in which an acoustic radiation force is used for remote palpation to generate localized tissue displacements, which are directly correlated to localized variations of tissue stiffness and are measured using a light probe in the same direction of ultrasound propagation. The experimental geometry has provision to input light beam along the ultrasound propagation direction, and hence it can be prealigned to ensure proper interception of the focal region by the light beam. Tissue-mimicking phantoms with homogeneous and isotropic mechanical properties of normal and malignant breast tissue are considered for the study. Each phantom is insonified by a focusing ultrasound transducer (1 MHz). The focal volume of the transducer and the ultrasound radiation force in the region are estimated through solving acoustic wave propagation through medium assuming average acoustic properties. The forward elastography problem is solved for the region of insonification assuming the Lame's parameters and Poisson's ratio, under Dirichlet boundary conditions which gives a distribution of displacement vectors. The direction of displacement, though presented spatial variation, is predominantly towards the ultrasound propagation direction. Using Monte Carlo (MC) simulation we have traced the photons through the phantom and collected the photons arriving at the detector on the boundary of the object in the direction of ultrasound. The intensity correlations are then computed from detected photons. The intensity correlation function computed through MC simulation showed a modulation whose strength is found to be proportional to the amplitude of displacement and inversely related to the storage (elastic) modulus. It is observed that when the storage modulus in the focal region is increased the computed displacement magnitude, as indicated by the depth of modulation in the intensity autocorrelation, decreased and the trend is approximately exponential.

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Modern wireline and wireless communication devices are multimode and multifunctional communication devices. In order to support multiple standards on a single platform, it is necessary to develop a reconfigurable architecture that can provide the required flexibility and performance. The Channel decoder is one of the most compute intensive and essential elements of any communication system. Most of the standards require a reconfigurable Channel decoder that is capable of performing Viterbi decoding and Turbo decoding. Furthermore, the Channel decoder needs to support different configurations of Viterbi and Turbo decoders. In this paper, we propose a reconfigurable Channel decoder that can be reconfigured for standards such as WCDMA, CDMA2000, IEEE802.11, DAB, DVB and GSM. Different parameters like code rate, constraint length, polynomials and truncation length can be configured to map any of the above mentioned standards. A multiprocessor approach has been followed to provide higher throughput and scalable power consumption in various configurations of the reconfigurable Viterbi decoder and Turbo decoder. We have proposed A Hybrid register exchange approach for multiprocessor architecture to minimize power consumption.

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Back face strain (BFS) measurement is now well-established as an indirect technique to monitor crack length in compact tension (CT) fracture specimens [1,2]. Previous work [2] developed empirical relations between fatigue crack propagation (FCP) parameters. BFS, and number of cycles for CT specimens subjected to constant amplitude fatigue loading. These predictions are experimentally validated in terms of the variations of mean values of BFS and load as a function of crack length. Another issue raised by this study concerns the validity of assigning fixed values for the Paris parameters C and n to describe FCP in realistic materials.

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The presence and orientation of remote double bonds are shown to completely alter the shapes of Cope rearrangement energy profiles in a heptacyclic system.

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Resistivity imaging of a reconfigurable phantom with circular inhomogeneities is studied with a simple instrumentation and data acquisition system for Electrical Impedance Tomography. The reconfigurable phantom is developed with stainless steel electrodes and a sinusoidal current of constant amplitude is injected to the phantom boundary using opposite current injection protocol. Nylon and polypropylene cylinders with different cross sectional areas are kept inside the phantom and the boundary potential data are collected. The instrumentation and the data acquisition system with a DIP switch-based multiplexer board are used to inject a constant current of desired amplitude and frequency. Voltage data for the first eight current patterns (128 voltage data) are found to be sufficient to reconstruct the inhomogeneities and hence the acquisition time is reduced. Resistivity images are reconstructed from the boundary data for different inhomogeneity positions using EIDORS-2D. The results show that the shape and resistivity of the inhomogeneity as well as the background resistivity are successfully reconstructed from the potential data for single or double inhomogeneity phantoms. The resistivity images obtained from the single and double inhomogeneity phantom clearly indicate the inhomogeneity as the high resistive material. Contrast to noise ratio (CNR) and contrast recovery (CR) of the reconstructed images are found high for the inhomogeneities near all the electrodes arbitrarily chosen for the entire study. (C) 2010 Elsevier Ltd. All rights reserved.

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In the Himalayas, a large area is covered by glaciers and seasonal snow and changes in its extent can influence availability of water in the Himalayan Rivers. In this paper, changes in glacial extent, glacial mass balance and seasonal snow cover are discussed. Glacial retreat was estimated for 1868 glaciers in 11 basins distributed in the Indian Himalaya since 1962. The investigation has shown an overall reduction in glacier area from 6332 to 5329km2 from 1962 to 2001/2 - an overall deglaciation of 16%. Snow line at the end of ablation season on the Chhota Shigri glacier observed using field and satellite methods suggests a change in altitude from 4900 to 5200m from the late 1970s to present. Seasonal snow cover was monitored in the 28 river sub-basins using normalized difference snow index (NDSI) technique in Central and Western Himalaya. The investigation has shown that in the early part of winter, i.e. from October to December, a large amount of snow retreat was observed. For many basins located in lower altitude and in the south of the Pir Panjal range, snow ablation was observed throughout the winter season. In addition, average stream runoff of the Baspa basin for the month of December increased by 75%. This combination of glacial retreat, negative mass balance, early melting of seasonal snow cover and winter-time increase in stream runoff might suggest an influence of global warming on the Himalayan cryosphere.

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pi-Face selectivities in electrophilic additiions (typically CCl2) to 7-methylenenorbornenes and 7-isopropylidenenorbornenes are modulated by endo-substituents.

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This paper presents a fast algorithm for data exchange in a network of processors organized as a reconfigurable tree structure. For a given data exchange table, the algorithm generates a sequence of tree configurations in which the data exchanges are to be executed. A significant feature of the algorithm is that each exchange is executed in a tree configuration in which the source and destination nodes are adjacent to each other. It has been proved in a theorem that for every pair of nodes in the reconfigurable tree structure, there always exists two and only two configurations in which these two nodes are adjacent to each other. The algorithm utilizes this fact and determines the solution so as to optimize both the number of configurations required and the time to perform the data exchanges. Analysis of the algorithm shows that it has linear time complexity, and provides a large reduction in run-time as compared to a previously proposed algorithm. This is well-confirmed from the experimental results obtained by executing a large number of randomly-generated data exchange tables. Another significant feature of the algorithm is that the bit-size of the routing information code is always two bits, irrespective of the number of nodes in the tree. This not only increases the speed of the algorithm but also results in simpler hardware inside each node.