Latency, Power and Performance Trade-offs in Network-on-Chips by Link Microarchitecture Exploration

This paper presents a power, latency and throughput trade-off study on NoCs by varying microarchitectural (e.g. pipelining) and circuit level (e.g. frequency and voltage) parameters. We change pipelining depth, operating frequency and supply voltage for 3 example NoCs - 16 node 2D Torus, Tree network and Reduced 2D Torus. We use an in-house NoC exploration framework capable of topology generation and comparison using parameterized models of Routers and links developed in SystemC. The framework utilizes interconnect power and delay models from a low-level modelling tool called Intacte[1]1. We find that increased pipelining can actually reduce latency. We also find that there exists an optimal degree of pipelining which is the most energy efficient in terms of minimizing energy-delay product.

Evidence for H2O2 as the product of reduction of oxygen by alternative oxidase in mitochondria from potato tubers

Oxygen Consumption by alternative oxidase (AOX), present in mitochondria of many angiosperms, is known to be cyanide-resistant in contrast to cytochrome oxidase. Its activity in potato tuber (Solarium tuberosum L.) was induced following chilling treatment at 4 degrees C.About half of the total O-2 consumption of succinate oxidation in such mitochondria was found to be sensitive to SHAM, a known inhibitor of AOX activity. Addition of catalase to the reaction mixture of AOX during the reaction decreased the rate of SHAM-sensitive oxygen consumption by nearly half, and addition at the end of the reaction released nearly half of the consumed oxygen by AOX, both typical of catalase action on H2O2. These findings with catalase suggest that the product of reduction of AOX is H2O2 and not H2O, as previously Surmised. In potatoes Subjected to chill stress (4 degrees C) for periods of 3, 5 and >= 8 days the activity of AOX in mitochondria increased progressively with a corresponding increase in the AOX protein detected by immunoblot of the protein.

Fault-Tolerant Average Execution Time Optimization for General Purpose Multi-Processor System-on Chips

Fault-tolerance is due to the semiconductor technology development important, not only for safety-critical systems but also for general-purpose (non-safety critical) systems. However, instead of guaranteeing that deadlines always are met, it is for general-purpose systems important to minimize the average execution time (AET) while ensuring fault-tolerance. For a given job and a soft (transient) error probability, we define mathematical formulas for AET that includes bus communication overhead for both voting (active replication) and rollback-recovery with checkpointing (RRC). And, for a given multi-processor system-on-chip (MPSoC), we define integer linear programming (ILP) models that minimize AET including bus communication overhead when: (1) selecting the number of checkpoints when using RRC, (2) finding the number of processors and job-to-processor assignment when using voting, and (3) defining fault-tolerance scheme (voting or RRC) per job and defining its usage for each job. Experiments demonstrate significant savings in AET.

Microstructure and damping behaviour of consolidated magnesium chips

Chips produced by turning a commercial grade pure magnesium billet were consolidated by solid state recycling technique of cold compaction followed by hot extrusion. The cold compacted billets were extruded at four different temperatures: 250 degrees C, 300 degrees C, 350 degrees C and 400 degrees C. For the purpose of comparison, cast magnesium (pure) billets were extruded under similar conditions. Extruded products were characterized for damping properties. Damping capacity and dynamic modulus was measured as a function of time and temperature at a fixed frequency of 5 Hz 10 to 14% increase in damping capacity was observed in chip consolidated products compared to reference material. Microstructural changes after the temperature sweep tests were examined. Chip boundaries present in consolidated products were observed to suppress grain coarsening which otherwise was significant in reference material. The present work is significant from the viewpoint of recycling of machined chips and development of sustainable manufacturing processes. (C) 2012 Elsevier B.V. All rights reserved.

Microstructure and tensile properties of consolidated magnesium chips

In this study tensile properties of consolidated magnesium chips obtained from solid state re-cycling (SSR) has been examined and correlated with the microstructure. Chips machined from as-cast billet of pure magnesium were consolidated through SSR technique, comprising of compaction at ambient conditions followed by hot extrusion at four different temperatures viz., 250, 300, 350 and 400 degrees C. The extruded rods were characterized for microstructure and their room temperature tensile properties. Both ultimate tensile strength and 0.2% proof stress of these consolidated materials are higher by 15-35% compared to reference material (as cast and extruded). Further these materials obey Hall-Petch relation with respect to strength dependence of grain size. Strain hardening behavior, measured in terms of hardening exponent, hardening capacity and hardening rate was found to be distinctly different in chip consolidated material compared to reference material. Strength asymmetry, measured as a ratio of compressive proof stress to tensile proof stress was higher in chip consolidated material. (C) 2012 Elsevier B.V. All rights reserved.

Influence of tool rake angle on the quality of pure magnesium chip-consolidated product

Chips were produced by orthogonal Cutting of cast pure magnesium billet with three different tool rake angles viz., -15 degrees, -5 degrees and +15 degrees on a lathe. Chip consolidation by solid state recycling technique involved cold compaction followed by hot extrusion. The extruded products were characterized for microstructure and mechanical properties. Chip-consolidated products from -15 degrees rake angle tools showed 19% increase in tensile strength, 60% reduction ingrain size and 12% increase in hardness compared to +15 degrees rake chip-consolidated product indicating better chip bonding and grain refinement. Microstructure of the fracture specimen Supports the abovefinding. On the overall, the present work high lights the importance of tool take angle in determining the quality of the chip-consolidated products. (C) 2009 Elsevier B.V. All rights reserved.

Design of multiunit electronic exchanges through decomposition

In this paper, we exploit the idea of decomposition to match buyers and sellers in an electronic exchange for trading large volumes of homogeneous goods, where the buyers and sellers specify marginal-decreasing piecewise constant price curves to capture volume discounts. Such exchanges are relevant for automated trading in many e-business applications. The problem of determining winners and Vickrey prices in such exchanges is known to have a worst-case complexity equal to that of as many as (1 + m + n) NP-hard problems, where m is the number of buyers and n is the number of sellers. Our method proposes the overall exchange problem to be solved as two separate and simpler problems: 1) forward auction and 2) reverse auction, which turns out to be generalized knapsack problems. In the proposed approach, we first determine the quantity of units to be traded between the sellers and the buyers using fast heuristics developed by us. Next, we solve a forward auction and a reverse auction using fully polynomial time approximation schemes available in the literature. The proposed approach has worst-case polynomial time complexity. and our experimentation shows that the approach produces good quality solutions to the problem. Note to Practitioners- In recent times, electronic marketplaces have provided an efficient way for businesses and consumers to trade goods and services. The use of innovative mechanisms and algorithms has made it possible to improve the efficiency of electronic marketplaces by enabling optimization of revenues for the marketplace and of utilities for the buyers and sellers. In this paper, we look at single-item, multiunit electronic exchanges. These are electronic marketplaces where buyers submit bids and sellers ask for multiple units of a single item. We allow buyers and sellers to specify volume discounts using suitable functions. Such exchanges are relevant for high-volume business-to-business trading of standard products, such as silicon wafers, very large-scale integrated chips, desktops, telecommunications equipment, commoditized goods, etc. The problem of determining winners and prices in such exchanges is known to involve solving many NP-hard problems. Our paper exploits the familiar idea of decomposition, uses certain algorithms from the literature, and develops two fast heuristics to solve the problem in a near optimal way in worst-case polynomial time.

Power Optimal Network-on-Chip Interconnect Design

A large part of today's multi-core chips is interconnect. Increasing communication complexity has made essential new strategies for interconnects, such as Network on Chip. Power dissipation in interconnects has become a substantial part of the total power dissipation. Techniques to reduce interconnect power have thus become a necessity. In this paper, we present a design methodology that gives values of bus width for interconnect links, frequency of operation for routers, in Network on Chip scenario that satisfy required throughput and dissipate minimal switching power. We develop closed form analytical expressions for the power dissipation, with bus width and frequency as variables and then use Lagrange multiplier method to arrive at the optimal values. We present a 4 port router in 90 nm technology library as case study. The results obtained from analysis are discussed.

A systolic evaluator for linear, quadratic, and cubic expressions

High-speed evaluation of a large number of linear, quadratic, and cubic expressions is very important for the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have actually been built by H. Fuchs and his group to evaluate linear expressions. In this paper, we describe a topological variant of Fuchs' pixel planes which can evaluate linear, quadratic, cubic, and higher-order polynomials. In our design, we make use of local interconnections only, i.e., interconnections between neighboring processing cells. This leads to the concept of tiling the processing cells for VLSI implementation.

Lubricated Tribology of a Eutectic Aluminium-Silicon Alloy in the Ultra-Mild Wear and Mild Wear Regimes for Long Sliding Times

Aluminium-silicon alloy, an important material used for the construction of internal combustion engines, exhibit pressure induced distinct regimes of wear and friction; ultra-mild and mild. In this work the alloy is slid lubricated against a spherical steel pin at contact pressures characteristic of the two test regimes, at a very low sliding velocity. In both cases, the friction is controlled at the initial stages of sliding by the abrasion of the steel pin by the protruding silicon particles of the disc. The generation of nascent steel chips helps to breakdown the additive in the oil by a cationic exchange that yields chemical products of benefits to the tribology. The friction is initially controlled by abrasion, but the chemical products gain increasing importance in controlling friction with sliding time. After long times, depending on contact pressure, the chemical products determine sliding friction exclusively. In this paper, a host of mechanical and spectroscopic techniques are used to identify and characterize mechanical damage and chemical changes. Although the basic dissipation mechanisms are the same in the two regimes, the matrix remains practically unworn in the low-pressure ultra-mild wear regime. In the higher pressure regime at long sliding times a small but finite wear rate prevails. Incipient plasticity in the subsurface controls the mechanism of wear.

Reinstate hydrogen peroxide as the product of alternative oxidase of plant mitochondria

Chill treatment of potato tubers for 8 days induced mitochondrial O-2 consumption by cyanide-insensitive alternative oxidase (AOX). About half of the total O-2 consumption in such mitochondria was found to be sensitive to salicylhydroxamate (SHAM), a known inhibitor of AOX activity. Addition of catalase to the reaction mixture of AOX during the reaction decreased the rate of SHAM-sensitive O-2 consumption by nearly half, and addition at the end of the reaction released half of the O-2 consumed by AOX, both typical of catalase action on H2O2. This reaffirmed that the product of reduction of O-2 by plant AOX was H2O2 as found earlier and not H2O as reported in some recent reviews.

A Simple Programmable 2-Pulse Generator for Pulsed NMR NQR Applications

Programmable pulse generator (PPG) circuits using programmable interval timer chips are normally based on a PC or a microprocessor. We describe here a simple low cost programmable two-pulse generator using Intel 8253s in a stand-alone mode, eliminating the need for a PC or a microprocessor, though our design also can be operated via a PC or a microprocessor.

Stability and throughput analysis of unslotted CDMA-ALOHA with finite number of users and code sharing

We consider a system comprising a finite number of nodes, with infinite packet buffers, that use unslotted ALOHA with Code Division Multiple Access (CDMA) to share a channel for transmitting packetised data. We propose a simple model for packet transmission and retransmission at each node, and show that saturation throughput in this model yields a sufficient condition for the stability of the packet buffers; we interpret this as the capacity of the access method. We calculate and compare the capacities of CDMA-ALOHA (with and without code sharing) and TDMA-ALOHA; we also consider carrier sensing and collision detection versions of these protocols. In each case, saturation throughput can be obtained via analysis pf a continuous time Markov chain. Our results show how saturation throughput degrades with code-sharing. Finally, we also present some simulation results for mean packet delay. Our work is motivated by optical CDMA in which "chips" can be optically generated, and hence the achievable chip rate can exceed the achievable TDMA bit rate which is limited by electronics. Code sharing may be useful in the optical CDMA context as it reduces the number of optical correlators at the receivers. Our throughput results help to quantify by how much the CDMA chip rate should exceed the TDMA bit rate so that CDMA-ALOHA yields better capacity than TDMA-ALOHA.