A systolic evaluator for linear, quadratic, and cubic expressions


Autoria(s): Mathias, PC; Patnaik, LM
Data(s)

01/12/1988

Resumo

High-speed evaluation of a large number of linear, quadratic, and cubic expressions is very important for the modeling and real-time display of objects in computer graphics. Using VLSI techniques, chips called pixel planes have actually been built by H. Fuchs and his group to evaluate linear expressions. In this paper, we describe a topological variant of Fuchs' pixel planes which can evaluate linear, quadratic, cubic, and higher-order polynomials. In our design, we make use of local interconnections only, i.e., interconnections between neighboring processing cells. This leads to the concept of tiling the processing cells for VLSI implementation.

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/32046/1/systolic.pdf

Mathias, PC and Patnaik, LM (1988) A systolic evaluator for linear, quadratic, and cubic expressions. In: Journal of Parallel and Distributed Computing, 5 (6). 729 -740.

Publicador

Elsevier science

Relação

http://dx.doi.org/10.1016/0743-7315(88)90039-1

http://eprints.iisc.ernet.in/32046/

Palavras-Chave #Computer Science & Automation (Formerly, School of Automation) #Sophisticated Instruments Facility
Tipo

Journal Article

PeerReviewed