Influence of adhesive non-linearities on the performance and optimal length of adhesive bonded joints

An analytical study for the static strength of adhesive lap joints is presented. The earlier solutions of Volkersen [i], DeBruyne[2] and others were limited to linear adhesives. The influence of adhesive non-linearity was first considered by Grimes' et al[3] and Dickson et al [4]. Recently Hart-Smith[5] successfully introduced elastic-plastic behaviour of the adhesive. In the present study the problem is formulated for general non-linear adhesive behaviour and an efficient numerical algorithm is written for the solution. Bilinear and trilinear models for the nonlinearity yield closed form analytical solutions.

Composite Performance and Reliability Analysis for Hypercube Systems

In this paper we propose a novel technique to model and ana¿ lyze the performability of parallel and distributed architectures using GSPN-reward models.

Performance and scaling of a 1.2 V/1.5 Ah nickel/metal hydride cell to a 6 V/1.5 Ah battery

A 1.2 V/1.5 Ah positive-limited nickel/metal hydride cell has been studied to determine its charge-discharge characteristics at different rates in conjunction with its AC impedance data. The faradaic efficiency of the cell is found to be maximum at similar to 70% charge input. The cell has been scaled to a 6 V/1.5 Ah battery. The cycle-life data on the battery suggest that it can sustain a prolonged charge-discharge schedule with little deterioration in its performance.

Performance and variability trade-off with gate-to-source/drain overlap length

The impact of gate-to-source/drain overlap length on performance and variability of 65 nm CMOS is presented. The device and circuit variability is investigated as a function of three significant process parameters, namely gate length, gate oxide thickness, and halo dose. The comparison is made with three different values of gate-to-source/drain overlap length namely 5 nm, 0 nm, and -5 nm and at two different leakage currents of 10 nA and 100 nA. The Worst-Case-Analysis approach is used to study the inverter delay fluctuations at the process corners. The drive current of the device for device robustness and stage delay of an inverter for circuit robustness are taken as performance metrics. The design trade-off between performance and variability is demonstrated both at the device level and circuit level. It is shown that larger overlap length leads to better performance, while smaller overlap length results in better variability. Performance trades with variability as overlap length is varied. An optimal value of overlap length of 0 nm is recommended at 65 nm gate length, for a reasonable combination of performance and variability.

Row-buffer reorganization: simultaneously improving performance and reducing energy in DRAMs

In this paper, based on the temporal and spatial locality characteristics of memory accesses in multicores, we propose a re-organization of the existing single large row buffer in a DRAM bank into multiple smaller row-buffers. The proposed configuration helps improve the row hit rates and also brings down the energy required for row-activations. The major contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves performance by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. Additionally, we introduce a Need Based Allocation scheme for buffer management that shows additional performance improvement.

Performance and reliability of Gd2O3 and stacked Gd2O3-Eu2O3 metal-insulator-metal capacitors

Gd2O3-based metal-insulator-metal capacitors have been characterized with single layer (Gd2O3) and bilayer (Gd2O3/Eu2O3 and Eu2O3/Gd2O3) stacks for analog and DRAM applications. Although single layer Gd2O3 capacitors provide highest capacitance density (15 fF/mu m(2)), they suffer from high leakage current density, poor capacitance density-voltage linearity, and reliability. The stacked dielectrics help to reduce leakage current density (1.2x10(-5) A/cm(2) and 2.7 x 10(-5) A/cm(2) for Gd2O3/Eu2O3 and Eu2O3/Gd2O3, respectively, at -1 V), improve quadratic voltage coefficient of capacitance (331 ppm/V-2 and 374 ppm/V-2 for Gd2O3/Eu2O3 and Eu2O3/Gd2O3, respectively, at 1 MHz), and improve reliability, with a marginal reduction in capacitance density. This is attributed to lower trap heights as determined from Poole-Frenkel conduction mechanism, and lower defect density as determined from electrode polarization model.

Supplier selection based on supply chain ecosystem, performance and risk criteria

A supply chain ecosystem consists of the elements of the supply chain and the entities that influence the goods, information and financial flows through the supply chain. These influences come through government regulations, human, financial and natural resources, logistics infrastructure and management, etc., and thus affect the supply chain performance. Similarly, all the ecosystem elements also contribute to the risk. The aim of this paper is to identify both performances-based and risk-based decision criteria, which are important and critical to the supply chain. A two step approach using fuzzy AHP and fuzzy technique for order of preference by similarity to ideal solution has been proposed for multi-criteria decision-making and illustrated using a numerical example. The first step does the selection without considering risks and then in the next step suppliers are ranked according to their risk profiles. Later, the two ranks are consolidated into one. In subsequent section, the method is also extended for multi-tier supplier selection. In short, we are presenting a method for the design of a resilient supply chain, in this paper.

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities

The twin demands of energy-efficiency and higher performance on DRAM are highly emphasized in multicore architectures. A variety of schemes have been proposed to address either the latency or the energy consumption of DRAMs. These schemes typically require non-trivial hardware changes and end up improving latency at the cost of energy or vice-versa. One specific DRAM performance problem in multicores is that interleaved accesses from different cores can potentially degrade row-buffer locality. In this paper, based on the temporal and spatial locality characteristics of memory accesses, we propose a reorganization of the existing single large row-buffer in a DRAM bank into multiple sub-row buffers (MSRB). This re-organization not only improves row hit rates, and hence the average memory latency, but also brings down the energy consumed by the DRAM. The first major contribution of this work is proposing such a reorganization without requiring any significant changes to the existing widely accepted DRAM specifications. Our proposed reorganization improves weighted speedup by 35.8%, 14.5% and 21.6% in quad, eight and sixteen core workloads along with a 42%, 28% and 31% reduction in DRAM energy. The proposed MSRB organization enables opportunities for the management of multiple row-buffers at the memory controller level. As the memory controller is aware of the behaviour of individual cores it allows us to implement coordinated buffer allocation schemes for different cores that take into account program behaviour. We demonstrate two such schemes, namely Fairness Oriented Allocation and Performance Oriented Allocation, which show the flexibility that memory controllers can now exploit in our MSRB organization to improve overall performance and/or fairness. Further, the MSRB organization enables additional opportunities for DRAM intra-bank parallelism and selective early precharging of the LRU row-buffer to further improve memory access latencies. These two optimizations together provide an additional 5.9% performance improvement.

Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Surface treatments for pistons and their effect on engine performance

Surface treatment alters the frictional behaviour of pistons in I.C. engines and can be used to improve engine performance. Surface treatments applied to aluminium alloy pistons of a high speed diesel engine and their effect on the engine performance are described. Certain piston surface treatments improve engine performance and also reduce the run-in period.

Impact of dust on solar photovoltaic (PV) performance: Research status, challenges and recommendations

The peaking of most oil reserves and impending climate change are critically driving the adoption of solar photovoltaic's (PV) as a sustainable renewable and eco-friendly alternative. Ongoing material research has yet to find a breakthrough in significantly raising the conversion efficiency of commercial PV modules. The installation of PV systems for optimum yield is primarily dictated by its geographic location (latitude and available solar insolation) and installation design (tilt, orientation and altitude) to maximize solar exposure. However, once these parameters have been addressed appropriately, there are other depending factors that arise in determining the system performance (efficiency and output). Dust is the lesser acknowledged factor that significantly influences the performance of the PV installations. This paper provides an appraisal on the current status of research in studying the impact of dust on PV system performance and identifies challenges to further pertinent research. A framework to understand the various factors that govern the settling/assimilation of dust and likely mitigation measures have been discussed in this paper. (C) 2010 Elsevier Ltd. All rights reserved.

Performance prediction and loss analysis of low specific speed submersible pumps

A performance prediction procedure is presented for low specific speed submersible pumps with a review of loss models given in the literature. Most of the loss theories discussed in this paper are one dimensional and improvements are made with good empiricism for the prediction to cover the entire range of operation of the low specific speed pumps. Loss correlations, particularly in the low flow range, are discussed. Prediction of the shape of efficiency-capacity and total head-capacity curves agrees well with the experimental results in almost the full range of operating conditions. The approach adopted in the present analysis, of estimating the losses in the individual components of a pump, provides means for improving the performance and identifying the problem areas in existing designs of the pumps. The investigation also provides a basis for selection of parameters for the optimal design of the pumps in which the maximum efficiency is an important design parameter. The scope for improvement in the prediction procedure with the nature of flow phenomena in the low flow region has been discussed in detail.

Pipelined ring algorithm for matrix multiplication on transputer networks: performance analysis and estimation

A parallel matrix multiplication algorithm is presented, and studies of its performance and estimation are discussed. The algorithm is implemented on a network of transputers connected in a ring topology. An efficient scheme for partitioning the input matrices is introduced which enables overlapping computation with communication. This makes the algorithm achieve near-ideal speed-up for reasonably large matrices. Analytical expressions for the execution time of the algorithm have been derived by analysing its computation and communication characteristics. These expressions are validated by comparing the theoretical results of the performance with the experimental values obtained on a four-transputer network for both square and irregular matrices. The analytical model is also used to estimate the performance of the algorithm for a varying number of transputers and varying problem sizes. Although the algorithm is implemented on transputers, the methodology and the partitioning scheme presented in this paper are quite general and can be implemented on other processors which have the capability of overlapping computation with communication. The equations for performance prediction can also be extended to other multiprocessor systems.

Extended histories: improving regularity and performance in correlation prefetchers

Data Prefetchers identify and make use of any regularity present in the history/training stream to predict future references and prefetch them into the cache. The training information used is typically the primary misses seen at a particular cache level, which is a filtered version of the accesses seen by the cache. In this work we demonstrate that extending the training information to include secondary misses and hits along with primary misses helps improve the performance of prefetchers. In addition to empirical evaluation, we use the information theoretic metric entropy, to quantify the regularity present in extended histories. Entropy measurements indicate that extended histories are more regular than the default primary miss only training stream. Entropy measurements also help corroborate our empirical findings. With extended histories, further benefits can be achieved by triggering prefetches during secondary misses also. In this paper we explore the design space of extended prefetch histories and alternative prefetch trigger points for delta correlation prefetchers. We observe that different prefetch schemes benefit to a different extent with extended histories and alternative trigger points. Also the best performing design point varies on a per-benchmark basis. To meet these requirements, we propose a simple adaptive scheme that identifies the best performing design point for a benchmark-prefetcher combination at runtime. In SPEC2000 benchmarks, using all the L2 accesses as history for prefetcher improves the performance in terms of both IPC and misses reduced over techniques that use only primary misses as history. The adaptive scheme improves the performance of CZone prefetcher over Baseline by 4.6% on an average. These performance gains are accompanied by a moderate reduction in the memory traffic requirements.