Medium-Coupled Bus-Based INS-GPS Sensor Fusion for Accurate and Reliable Positioning

A scheme for integration of stand-alone INS and GPS sensors is presented, with data interchange over an external bus. This ensures modularity and sensor interchangeability. Use of a medium-coupled scheme reduces data flow and computation, facilitating use in surface vehicles. Results show that the hybrid navigation system is capable of delivering high positioning accuracy.

Parallel polygon scan conversion algorithms: Performance evaluation on a shared bus architecture

In this paper, three parallel polygon scan conversion algorithms have been proposed, and their performance when executed on a shared bus architecture has been compared. It has been shown that the parallel algorithm that does not use edge coherence performs better than those that use edge coherence. Further, a multiprocessing architecture has been proposed to execute the parallel polygon scan conversion algorithms more efficiently than a single shared bus architecture.

Design and evaluation of a dual-microcomputer shared memory system with a shared I/O bus

The design, implementation and evaluation are described of a dual-microcomputer system based on the concept of shared memory. Shared memory is useful for passing large blocks of data and it also provides a means to hold and work with shared data. In addition to the shared memory, a separate bus between the I/O ports of the microcomputers is provided. This bus is utilized for interprocessor synchronization. Software routines helpful in applying the dual-microcomputer system to realistic problems are presented. Performance evaluation of the system is carried out using benchmarks.

Harmonic Analysis of Advanced Bus-Clamping PWM Techniques

Special switching sequences can be employed in space-vector-based generation of pulsewidth-modulated (PWM) waveforms for voltage-source inverters. These sequences involve switching a phase twice, switching the second phase once, and clamping the third phase in a subcycle. Advanced bus-clamping PWM (ABCPWM) techniques have been proposed recently that employ such switching sequences. This letter studies the spectral properties of the waveforms produced by these PWM techniques. Further, analytical closed-form expressions are derived for the total rms harmonic distortion due to these techniques. It is shown that the ABCPWM techniques lead to lower distortion than conventional space vector PWM and discontinuous PWM at higher modulation indexes. The findings are validated on a 2.2-kW constant $V/f$ induction motor drive and also on a 100-kW motor drive.

Study of voltage collapse at converter bus in asynchronous MTDC-AC systems

This paper presents the analysis and study of voltage collapse at any converter bus in an AC system interconnected by multiterminal DC (MTDC) links. The analysis is based on the use of the voltage sensitivity factor (VSF) as a voltage collapse proximity indicator (VCPI). In this paper the VSF is defined as a matrix which is applicable to MTDC systems. The VSF matrix is derived from the basic steady state equations of the converter, control, DC and AC networks. The structure of the matrix enables the derivation of some of the basic properties which are generally applicable. A detailed case study of a four-terminal MTDC system is presented to illustrate the effects of control strategies at the voltage setting terminal (VST) and other terminals. The controls considered are either constant angle, DC voltage, AC voltage, reactive current and reactive power at the VST and constant power or current at the other terminals. The effect of the strength of the AC system (measured by short circuit ratio) on the VSF is investigated. Several interesting and new results are presented. An analytical expression for the self VSF at VST is also derived for some specific cases which help to explain the number of transitions in VSF around the critical values of SCR.

Recommendations for driver licensing and traffic law enforcement in India aiming to improve road safety

During the last decade, developing countries such as India have been exhibiting rapid increase in human population and vehicles, and increase in road accidents. Inappropriate driving behaviour is considered one of the major causes of road accidents in India as compared to defective geometric design of pavement or mechanical defects in vehicles. It can result in conditions such as lack of lane discipline, disregard to traffic laws, frequent traffic violations, increase in crashes due to self-centred driving, etc. It also demotivates educated drivers from following good driving practices. Hence, improved driver behaviour can be an effective countermeasure to reduce the vulnerability of road users and inhibit crash risks. This article highlights improved driver behaviour through better driver education, driver training and licensing procedures along with good on-road enforcement; as an effective countermeasure to ensure road safety in India. Based on the review and analysis, the article also recommends certain measures pertaining to driver licensing and traffic law enforcement in India aimed at improving road safety.

Common mode DC bus filter for Active Front-End converter

Active Front-End (AFE) converter operation produces electrically noisy DC bus on common mode basis. This results in higher ground current as compared to three phase diode bridge rectifier. Filter topologies for DC bus have to deal problems with switching frequency and harmonic currents. The proposed filter approach reduces common mode voltage and circulates third harmonic current within the system, resulting in minimal ground current injection. The filtering technique, its constrains and design to attenuate common mode voltage and eliminate lower order harmonics injection to ground is discussed. The experimental results for operation of the converter with both SPWM and CSVPWM are presented.

CFD Based Design Optimizations of the Diffuser of a Gas Dynamically Driver Laser Cavity

Based on the an earlier CFD analysis of the performance of the gas-dynamically controlled laser cavity [1]it was found that there is possibility of optimizing the geometry of the diffuser that can bring about reductions in both size and cost of the system by examining the critical dimensional requirements of the diffuser. Consequently,an extensive CFD analysis has been carried out for a range of diffuser configurations by simulating the supersonic flow through the arrangement including the laser cavity driven by a bank of converging – diverging nozzles and the diffuser. The numerical investigations with 3D-RANS code are carried out to capture the flow patterns through diffusers past the cavity that has multiple supersonic jet interactions with shocks leading to complex flow pattern. Varying length of the diffuser plates is made to be the basic parameter of the study. The analysis reveals that the pressure recovery pattern during the flow through the diffuser from the simulation, being critical for the performance of the laser device shows its dependence on the diffuser length is weaker beyond a critical lower limit and this evaluation of this limit would provide a design guideline for a more efficient system configuration.The observation based on the parametric study shows that the pressure recovery transients in the near vicinity of the cavity is not affected for the reduction in the length of the diffuser plates up to its 10% of the initial size, indicating the design in the first configuration that was tested experimentally has a large factor of margin. The flow stability in the laser cavity is found to be unaffected since a strong and stable shock is located at the leading edge of the diffuser plates while the downstream shock and flow patterns are changed, as one would expect. Results of the study for the different lengths of diffusers in the range of 10% to its full length are presented, keeping the experimentally tested configuration used in the earlier study [1] as the reference length. The conclusions drawn from the analysis is found to be of significance since it provides new design considerations based on the understanding of the intricacies of the flow, allowing for a hardware optimization that can lead to substantial size reduction of the device with no loss of performance.

Space vector based bus clamped PWM algorithms for three level inverters: implementation, performance analysis and application considerations

This paper describes the different types of space vector based bus clamped PWM algorithms for three level inverters. A novel bus clamp PWM algorithm for low modulation indices region is also presented. The principles and switching sequences of all the types of bus clamped algorithms for high switching frequency are presented. Synchronized version of the PWM sequences for high power applications where switching frequency is low is also presented. The implementation details on DSP based digital controller and experimental results are presented. The THD of the output waveforms is studied for the entire operating region and is compared with the conventional space vector PWM technique. The bus clamped techniques can be used to reduce the switching losses or to improve the output voltage quality or both.. Different issues dominate depending on the type of application and power rating of the inverters. The results presented in this paper can be used for judicious use of the PWM techniques, which result in improved system efficiency and performance.

Experimental Investigation on the Effect of Advanced Bus-Clamping Pulsewidth Modulation on Motor Acoustic Noise

Voltage source inverters (VSIs) supply nonsinusoidal voltages to induction motor drives, leading to line current distortion and torque pulsation. Conventional space vector pulsewidth modulation (PWM) techniques are widely used in VSIs on the account of good waveform quality and high dc bus utilization. In a conventional space vector PWM technique, the switching sequence begins with one zero state and ends with the other zero state in a subcycle. Some novel switching sequences have been proposed, which employ only one zero state but apply one of the two active states twice in a subcycle. One pair of such special switching sequences has recently been shown to reduce the pulsating torque considerably. In this paper, the conventional and special switching sequences are compared experimentally in terms of acoustic noise. In the low-and medium-speed ranges, the special switching sequence is seen to reduce the amplitude of the tonal component of noise at the switching frequency considerably and is also found to result in spread spectrum.

Study on the Effect of Dead Time and its Compensation for Bus-Clamping PWM Techniques

Dead-time is provided in between the gating signals of the top and bottom semiconductor switches in an inverter leg to prevent the shorting of DC bus. Due to this dead time, there is a significant unwanted change in the output voltage of the inverter. The effect is different for different pulse width modulation (PWM) methodologies. The effect of dead-time on the output fundamental voltage is studied theoretically as well as experimentally for bus-clamping PWM methodologies. Further, experimental observations on the effectiveness of dead-time compensation are presented.

Analysis of the modulation process in advanced bus-clamping PWM techniques

Advanced bus-clamping pulse width modulation (ABCPWM) techniques are advantageous in terms of line current distortion and inverter switching loss in voltage source inverter-fed applications. However, the PWM waveforms corresponding to these techniques are not amenable to carrier-based generation. The modulation process in ABCPWM methods is analyzed here from a “per-phase” perspective. It is shown that three sets of descendant modulating functions (or modified modulating functions) can be generated from the three-phase sinusoidal signals. Each set of the modified modulating functions can be used to produce the PWM waveform of a given phase in a computationally efficient manner. Theoretical results and experimental investigations on a 5hp motor drive are presented

An Advanced Gate Driver for Insulated Gate Bipolar Transistors to Eliminate Dead-time Induced Distortions in Inverter Output

Dead-time is introduced between the gating signals to the top and bottom switches in a voltage source inverter (VSI) leg, to prevent shoot through fault due to the finite turn-off times of IGBTs. The dead-time results in a delay when the incoming device is an IGBT, resulting in error voltage pulses in the inverter output voltage. This paper presents the design, fabrication and testing of an advanced gate driver, which eliminates dead-time and consequent output distortion. Here, the gating pulses are generated such that the incoming IGBT transition is not delayed and shoot-through is also prevented. The various logic units of the driver card and fault tolerance of the driver are verified through extensive tests on different topologies such as chopper, half-bridge and full-bridge inverter, and also at different conditions of load. Experimental results demonstrate the improvement in the load current waveform quality with the proposed circuit, on account of elimination of dead-time.

Analytical evaluation of harmonic distortion factor corresponding to generalised advanced bus-clamping pulse width modulation

A few advanced bus-clamping pulse width modulation (ABCPWM) methods have been proposed recently for a three-phase inverter. With these methods, each phase is clamped, switched at nominal frequency, and switched at twice the nominal frequency in different regions of the fundamental cycle. This study proposes a generalised ABCPWM scheme, encompassing the few ABCPWM schemes that have been proposed and many more ABCPWM schemes that have not been reported yet. Furthermore, analytical closed-form expression is derived for the harmonic distortion factor corresponding to the generalised ABCPWM. This factor is independent of load parameters. The analytical expression derived here brings out the dependence of root-mean-square (RMS) current ripple on modulation index, and can be used to evaluate the RMS current ripple corresponding to any ABCPWM scheme. The analytical closed-form expression is validated experimentally in terms of measured weighted total harmonic distortion (THD) in line voltage (V-WTHD) and measured THD in line current (I-THD) on a 6 kW induction motor drive.