Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in R-ON and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Part II: A Fully Integrated RF PA in 28-nm CMOS With Device Design for Optimized Performance and ESD Robustness

In this paper, we report drain-extended MOS device design guidelines for the RF power amplifier (RF PA) applications. A complete RF PA circuit in a 28-nm CMOS technology node with the matching and biasing network is used as a test vehicle to validate the RF performance improvement by a systematic device design. A complete RF PA with 0.16-W/mm power density is reported experimentally. By simultaneous improvement of device-circuit performance, 45% improvement in the circuit RF power gain, 25% improvement in the power-added efficiency at 1-GHz frequency, and 5x improvement in the electrostatic discharge robustness are reported experimentally.

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Digital image analysis around isotropic points for photoelastic pattern recognition

Fringe tracking and fringe order assignment have become the central topics of current research in digital photoelasticity. Isotropic points (IPs) appearing in low fringe order zones are often either overlooked or entirely missed in conventional as well as digital photoelasticity. We aim to highlight image processing for characterizing IPs in an isochromatic fringe field. By resorting to a global analytical solution of a circular disk, sensitivity of IPs to small changes in far-field loading on the disk is highlighted. A local theory supplements the global closed-form solutions of three-, four-, and six-point loading configurations of circular disk. The local theoretical concepts developed in this paper are demonstrated through digital image analysis of isochromatics in circular disks subjected to three-and four-point loads. (C) 2015 Society of Photo-Optical Instrumentation Engineers (SPIE)

A 1 V supercapacitor device with nanostructured graphene oxide/polyaniline composite materials

Polyaniline and graphene oxide composite on activated carbon cum reduced graphene oxide-supported supercapacitor electrodes are fabricated and electrochemically characterized in a three-electrode cell assembly. Attractive supercapacitor performance, namely high-power capability and cycling stability for graphene oxide/polyaniline composite, is observed owing to the layered and porous-polymeric-structured electrodes. Based on the materials characterization data in a three-electrode cell assembly, 1 V supercapacitor devices are developed and performance tested. A comparative study has also been conducted for polyaniline and graphene oxide/polyaniline composite-based 1 V supercapacitors for comprehending the synergic effect of graphene oxide and polyaniline. Graphene oxide/polyaniline composite-based capacitor that exhibits about 100 F g(-1) specific capacitance with faradaic efficiency in excess of 90% has its energy and power density values of 14 Wh kg(-1) and 72 kW kg(-1), respectively. Cycle-life data for over 1000 cycles reflect 10% capacitance degradation for graphene oxide/polyaniline composite supercapacitor.

Part I: Physical Insights Into the Two-Stage Breakdown Characteristics of STI-Type Drain-Extended pMOS Device

In this paper, we study breakdown characteristics in shallow-trench isolation (STI)-type drain-extended MOSFETs (DeMOS) fabricated using a low-power 65-nm triple-well CMOS process with a thin gate oxide. Experimental data of p-type STI-DeMOS device showed distinct two-stage behavior in breakdown characteristics in both OFF-and ON-states, unlike the n-type device, causing a reduction in the breakdown voltage and safe operating area. The first-stage breakdown occurs due to punchthrough in the vertical structure formed by p-well, deep n-well, and p-substrate, whereas the second-stage breakdown occurs due to avalanche breakdown of lateral n-well/p-well junction. The breakdown characteristics are also compared with the STI-DeNMOS device structure. Using the experimental results and advanced TCAD simulations, a complete understanding of breakdown mechanisms is provided in this paper for STI-DeMOS devices in advanced CMOS processes.

Protection of Digital Telecom Exchanges Against Lightning Surges and Earth Faults

Low-power electronic devices used in digital telecom exchanges are vulnerable to surge voltages and currents primarily originating from natural lightning or due to the direct interactions between electric power and telecommunication lines, etc., causing the earth/ground potential rise, neutral potential rise, and faults in the system. The fault currents may flow directly to telecom lines or through the equipment to the customer's premises, causing adequate damage to the equipment and personnel safety. In wireline applications, analog or digital, central office, exchanges, and subscriber sides have to be protected. Decisive protection and protective methods have to be employed for proper functioning of the equipment under overvoltage/overcurrent conditions. Current investigation reports some interesting results obtained on the recently developed high-voltage high-current protection cards used in digital telecom exchanges. The performances of protection cards both for the ring wave and hybrid wave surges are evaluated and presented. The surge generators required for the investigation are developed and fabricated in house as per the relevant telecom standards.

Design of a Wearable Remote Neonatal Health Monitoring Device

In this text we present the design of a wearable health monitoring device capable of remotely monitoring health parameters of neonates for the first few weeks after birth. The device is primarily aimed at continuously tracking the skin temperature to indicate the onset of hypothermia in newborns. A medical grade thermistor is responsible for temperature measurement and is directly interfaced to a microcontroller with an integrated bluetooth low energy radio. An inertial sensor is also present in the device to facilitate breathing rate measurement which has been discussed briefly. Sensed data is transferred securely over bluetooth low energy radio to a nearby gateway, which relays the information to a central database for real time monitoring. Low power optimizations at both the circuit and software levels ensure a prolonged battery life. The device is packaged in a baby friendly, water proof housing and is easily sterilizable and reusable.

Nickel Electrode for Improving Current Density in Organic Electronic Device

In this work, polymer diode performance was analyzed by using nickel as anode electrode from two kinds of nickel as starting materials, namely nickel wire Ni{B} and nickel nano-particle Ni{N}. Metal electrode surface roughness and grain morphology were investigated by atomic force microscope and scanning electron microscope, respectively. Current-voltage (I-V) and capacitance-voltage (C-V) characteristics were measured for the fabricated device at room temperature. Obtained result from the current-voltage characteristics shows an increment in the current density for nickel nano-particle top electrode device. The increase in the current density could be due to a reduction in built-in voltage at P3HT/Ni{N} interface.

Curvature Management in Buffer Layer for Device Quality GaN Growth on Si (111)

An efficient buffer layer scheme has been designed to address the issue of curvature management during metalorganic chemical vapour deposition growth of GaN on Si (111) substrate. This is necessary to prevent cracking of the grown layer during post-growth cooling down from growth temperature to room temperature and to achieve an allowable bow (<40 m) in the wafer for carrying out lithographic processes. To meet both these ends simultaneously, the stress evolution in the buffer layers was observed carefully. The reduction in precursor flow during the buffer layer growth provided better control over curvature evolution in the growing buffer layers. This has enabled the growth of a suitable high electron mobility transistor (HEMT) stack on 2'' Si (111) substrate of 300 m thickness with a bow as low as 11.4 m, having a two-dimensional electron gas (2DEG) of mobility, carrier concentration, and sheet resistance values 1510 cm(2)/V-s, 0.96 x 10(13)/cm(2), and 444 /, respectively. Another variation of similar technique resulted in a bow of 23.4 m with 2DEG mobility, carrier concentration, and sheet resistance values 1960 cm(2)/V-s, 0.98 x 10(13)/cm(2), and 325 /, respectively.

A Deep-Blue Electroluminescent Device Based on a Coumarin Derivative

The design and synthesis is reported of 7-(9H-carbazol-9-yl)-4-methylcoumarin (Cz-Cm), comprising a carbazole donor moiety and a 4-methylcoumarin acceptor unit, for use in a blue organic light-emitting diode. A detailed solid state, theoretical and spectroscopic study was performed to understand the structure-property relationships. The material exhibits deep-blue emission and high photoluminescence quantum yield both in solution and in a doped matrix. A deep-blue electroluminescence emission at 430nm, a maximum brightness of 292cdm(-2) and an external quantum efficiency of 0.4% was achieved with a device configured as follows: ITO/NPD (30nm)/TCTA (20nm)/CzSi(10nm)/10wt% Cz-Cm:DPEPO (10nm)/TPBI (30nm)/LiF (1nm)/Al ITO=indium tin oxide, NPD=N,N-di(1-naphthyl)-N,N-diphenyl-(1,1-biphenyl)-4,4-diamine, TCTA=tris(4-carbazoyl-9-ylphenyl)amine, CzSi=9-(4-tert-butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole, DPEPO=bis2-(diphenylphosphino)phenyl]ether oxide, TPBI=1,3,5-tris(N-phenylbenzimidazol-2-yl)benzene].