Online client-AP association in WLANs

In many IEEE 802.11 WLAN deployments, wireless clients have a choice of access points (AP) to connect to. In current systems, clients associate with the access point with the strongest signal to noise ratio. However, such an association mechanism can lead to unequal load sharing, resulting in diminished system performance. In this paper, we first provide a numerical approach based on stochastic dynamic programming to find the optimal client-AP association algorithm for a small topology consisting of two access points. Using the value iteration algorithm, we determine the optimal association rule for the two-AP topology. Next, utilizing the insights obtained from the optimal association ride for the two-AP case, we propose a near-optimal heuristic that we call RAT. We test the efficacy of RAT by considering more realistic arrival patterns and a larger topology. Our results show that RAT performs very well in these scenarios as well. Moreover, RAT lends itself to a fairly simple implementation.

Lessons from the Sparse Sensor Network Deployment in Rural India

We discuss the key issues in the deployment of sparse sensor networks. The network monitors several environment parameters and is deployed in a semi-arid region for the benefit of small and marginal farmers. We begin by discussing the problems of an existing unreliable 1 sq km sparse network deployed in a village. The proposed solutions are implemented in a new cluster. The new cluster is a reliable 5 sq km network. Our contributions are two fold. Firstly, we describe a. novel methodology to deploy a sparse reliable data gathering sensor network and evaluate the ``safe distance'' or ``reliable'' distance between nodes using propagation models. Secondly, we address the problem of transporting data from rural aggregation servers to urban data centres. This paper tracks our steps in deploying a sensor network in a village,in India, trying to provide better diagnosis for better crop management. Keywords - Rural, Agriculture, CTRS, Sparse.

Influence of crossed electric and quantizing magnetic fields on the Einstein relation in nonlinear optical, optoelectronic and related materials: Simplified theory, relative comparison and suggestion for experimental determination

An attempt is made to study the Einstein relation for the diffusivity-to-mobility ratio (DMR) under crossed fields' configuration in nonlinear optical materials on the basis of a newly formulated electron dispersion law by incorporating the crystal field in the Hamiltonian and including the anisotropies of the effective electron mass and the spin-orbit splitting constants within the framework of kp formalisms. The corresponding results for III-V, ternary and quaternary compounds form a special case of our generalized analysis. The DMR has also been investigated for II-VI and stressed materials on the basis of various appropriate dispersion relations. We have considered n-CdGeAs2, n-Hg1-xCdxTe, n-In1-xGaxAsyP1-y lattice matched to InP, p-CdS and stressed n-InSb materials as examples. The DMR also increases with increasing electric field and the natures of oscillations are totally band structure dependent with different numerical values. It has been observed that the DMR exhibits oscillatory dependences with inverse quantizing magnetic field and carrier degeneracy due to the Subhnikov-de Haas effect. An experimental method of determining the DMR for degenerate materials in the present case has been suggested. (C) 2010 Elsevier B.V. All rights reserved.

A Simple Five-Level Inverter Topology for Induction Motor Drive Using Conventional Two-Level Inverters and Flying Capacitor Technique

This paper proposes a new five-level inverter topology for open-end winding induction motor (IM) drive. The popular existing circuit configurations for five-level inverter include the NPC inverter and flying capacitor topologies. Compared to the NPC inverter, the proposed topology eliminates eighteen clamping diodes having different voltage ratings in the present circuit. Moreover it requires only one capacitor bank per phase, whereas flying capacitor schemes for five level topologies require six capacitor banks per phase. The proposed topology is realized by feeding the phase winding of an open-end induction motor with two-level inverters in series with flying capacitors. The flying capacitor voltages are balanced using the switching state redundancy for full modulation range. The proposed inverter scheme is capable of producing two-level to five-level pulse width modulated voltage across the phase winding depending on the modulation range. Additionally, in case of any switch failure in the flying capacitor connection, the proposed inverter topology can be operated as a three-level inverter for full modulation range. The proposed scheme is experimentally verified on a four pole, 5hp induction motor drive.

Unified large and small signal non-quasi-static model for long channel symmetric DG MOSFET

We propose a unified model for large signal and small signal non-quasi-static analysis of long channel symmetric double gate MOSFET. The model is physics based and relies only on the very basic approximation needed for a charge-based model. It is based on the EKV formalism Enz C, Vittoz EA. Charge based MOS transistor modeling. Wiley; 2006] and is valid in all regions of operation and thus suitable for RF circuit design. Proposed model is verified with professional numerical device simulator and excellent agreement is found. (C) 2010 Elsevier Ltd. All rights reserved.

On the two-dimensional thermoelectric power in quantum wells of non-parabolic materials under magnetic quantization

We present a simplified theoretical formulation of the thermoelectric power (TP) under magnetic quantization in quantum wells (QWs) of nonlinear optical materials on the basis of a newly formulated magneto-dispersion law. We consider the anisotropies in the effective electron masses and the spin-orbit constants within the framework of k.p formalism by incorporating the influence of the crystal field splitting. The corresponding results for III-V materials form a special case of our generalized analysis under certain limiting conditions. The TP in QWs of Bismuth, II-VI, IV-VI and stressed materials has been studied by formulating appropriate electron magneto-dispersion laws. We also address the fact that the TP exhibits composite oscillations with a varying quantizing magnetic field in QWs of n-Cd3As2, n-CdGeAs2, n-InSb, p-CdS, stressed InSb, PbTe and Bismuth. This reflects the combined signatures of magnetic and spatial quantizations of the carriers in such structures. The TP also decreases with increasing electron statistics and under the condition of non-degeneracy, all the results as derived in this paper get transformed into the well-known classical equation of TP and thus confirming the compatibility test. We have also suggested an experimental method of determining the elastic constants in such systems with arbitrary carrier energy spectra from the known value of the TP. (C) 2010 Elsevier Ltd. All rights reserved.

Recent Advances and Industrial Applications of Multilevel Converters

Multilevel converters have been under research and development for more than three decades and have found successful industrial application. However, this is still a technology under development, and many new contributions and new commercial topologies have been reported in the last few years. The aim of this paper is to group and review these recent contributions, in order to establish the current state of the art and trends of the technology, to provide readers with a comprehensive and insightful review of where multilevel converter technology stands and is heading. This paper first presents a brief overview of well-established multilevel converters strongly oriented to their current state in industrial applications to then center the discussion on the new converters that have made their way into the industry. In addition, new promising topologies are discussed. Recent advances made in modulation and control of multilevel converters are also addressed. A great part of this paper is devoted to show nontraditional applications powered by multilevel converters and how multilevel converters are becoming an enabling technology in many industrial sectors. Finally, some future trends and challenges in the further development of this technology are discussed to motivate future contributions that address open problems and explore new possibilities.

A Five-Level Inverter Scheme for a Four-Pole Induction Motor Drive by Feeding the Identical Voltage-Profile Windings From Both Sides

This paper presents a five-level inverter scheme with four two-level inverters for a four-pole induction motor (IM) drive. In a conventional three-phase four-pole IM, there exists two identical voltage-profile winding coil groups per phase around the armature, which are connected in series and spatially apart by two pole pitches. In this paper, these two identical voltage-profile pole-pair winding coils in each phase of the IM are disconnected and fed from four two-level inverters from four sides of the windings with one-fourth dc-link voltage as compared to a conventional five-level neutral-point-clamped inverter. The scheme presented in this paper does not require any special design modification for the induction machine. For this paper, a four-pole IM drive is used, and the scheme can be easily extended to IMs with more than four poles. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

An efficient reduction algorithm for computation of interconnect delay variability for statistical timing analysis in clock tree planning

In this paper, we propose a novel and efficient algorithm for modelling sub-65 nm clock interconnect-networks in the presence of process variation. We develop a method for delay analysis of interconnects considering the impact of Gaussian metal process variations. The resistance and capacitance of a distributed RC line are expressed as correlated Gaussian random variables which are then used to compute the standard deviation of delay Probability Distribution Function (PDF) at all nodes in the interconnect network. Main objective is to find delay PDF at a cheaper cost. Convergence of this approach is in probability distribution but not in mean of delay. We validate our approach against SPICE based Monte Carlo simulations while the current method entails significantly lower computational cost.

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor-single electron transistor integrated circuits

For the first time, the impact of energy quantisation in single electron transistor (SET) island on the performance of hybrid complementary metal oxide semiconductor (CMOS)-SET transistor circuits has been studied. It has been shown through simple analytical models that energy quantisation primarily increases the Coulomb Blockade area and Coulomb Blockade oscillation periodicity of the SET device and thus influences the performance of hybrid CMOS-SET circuits. A novel computer aided design (CAD) framework has been developed for hybrid CMOS-SET co-simulation, which uses Monte Carlo (MC) simulator for SET devices along with conventional SPICE for metal oxide semiconductor devices. Using this co-simulation framework, the effects of energy quantisation have been studied for some hybrid circuits, namely, SETMOS, multiband voltage filter and multiple valued logic circuits. Although energy quantisation immensely deteriorates the performance of the hybrid circuits, it has been shown that the performance degradation because of energy quantisation can be compensated by properly tuning the bias current of the current-biased SET devices within the hybrid CMOS-SET circuits. Although this study is primarily done by exhaustive MC simulation, effort has also been put to develop first-order compact model for SET that includes energy quantisation effects. Finally, it has been demonstrated that one can predict the SET behaviour under energy quantisation with reasonable accuracy by slightly modifying the existing SET compact models that are valid for metallic devices having continuous energy states.

Interdiffusion studies in bulk Au-Ti system

The performance of the contacts, where Au/Ti layers are used in the metallization scheme, largely depends on the product phases grown by interdiffusion at the interface. It is found that four intermetallic compounds grow with narrow homogeneity range and wavy interfaces in the interdiffusion zone. The presence of wavy interfaces is the indication of high anisotropy in diffusion of the product phases. This also reflects in the deviation of parabolic growth from the average. Further, we have determined the relevant diffusion parameters, such as interdiffusion coefficient in the penetrated region of the end members and integrated diffusion coefficients of the intermetallic compounds.

Optimization and design of energy transport system for solar cooking application

This paper proposes a hybrid solar cooking system where the solar energy is transported to the kitchen. The thermal energy source is used to supplement the Liquefied Petroleum Gas (LPG) that is in common use in kitchens. Solar energy is transferred to the kitchen by means of a circulating fluid. Energy collected from sun is maximized by changing the flow rate dynamically. This paper proposes a concept of maximum power point tracking (MPPT) for the solar thermal collector. The diameter of the pipe is selected to optimize the overall energy transfer. Design and sizing of different components of the system are explained. Concept of MPPT is validated with simulation and experimental results. (C) 2010 Elsevier Ltd. All rights reserved.

A Hybrid Multilevel Inverter Topology for an Open-End Winding Induction-Motor Drive Using Two-Level Inverters in Series With a Capacitor-Fed H-Bridge Cell

In this paper, a new five-level inverter topology for open-end winding induction-motor (IM) drive is proposed. The open-end winding IM is fed from one end with a two-level inverter in series with a capacitor-fed H-bridge cell, while the other end is connected to a conventional two-level inverter. The combined inverter system produces voltage space-vector locations identical to that of a conventional five-level inverter. A total of 2744 space-vector combinations are distributed over 61 space-vector locations in the proposed scheme. With such a high number of switching state redundancies, it is possible to balance the H-bridge capacitor voltages under all operating conditions including overmodulation region. In addition to that, the proposed topology eliminates 18 clamping diodes having different voltage ratings compared with the neutral point clamped inverter. On the other hand, it requires only one capacitor bank per phase, whereas the flying-capacitor scheme for a five-level topology requires more than one capacitor bank per phase. The proposed inverter topology can be operated as a three-level inverter for full modulation range, in case of any switch failure in the capacitor-fed H-bridge cell. This will increase the reliability of the system. The proposed scheme is experimentally verified on a four-pole 5-hp IM drive.

A Non Quasi-Static Small Signal Model for Long Channel Symmetric DG MOSFET

We propose a compact model for small signal non quasi static analysis of long channel symmetric double gate MOSFET The model is based on the EKV formalism and is valid in all regions of operation and thus suitable for RF circuit design Proposed model is verified with professional numerical device simulator and excellent agreement is found well beyond the cut-off frequency

On Minimization of Test Application Time for RAS

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume