On Minimization of Test Application Time for RAS


Autoria(s): Adiga, Raghavendra; Arpit, Gandhi; Singh, Virendra; Saluja, Kewal K; Fujiwara, Hideo; Singh, Adit D
Data(s)

2010

Resumo

Conventional Random access scan (RAS) for testing has lower test application time, low power dissipation, and low test data volume compared to standard serial scan chain based design In this paper, we present two cluster based techniques, namely, Serial Input Random Access Scan and Variable Word Length Random Access Scan to reduce test application time even further by exploiting the parallelism among the clusters and performing write operations on multiple bits Experimental results on benchmarks circuits show on an average 2-3 times speed up in test write time and average 60% reduction in write test data volume

Formato

application/pdf

Identificador

http://eprints.iisc.ernet.in/34071/1/RAS.pdf

Adiga, Raghavendra and Arpit, Gandhi and Singh, Virendra and Saluja, Kewal K and Fujiwara, Hideo and Singh, Adit D (2010) On Minimization of Test Application Time for RAS. In: 23rd International Conference on VLSI Design/9th International Conference on Embedded Systems, JAN 03-07, 2010, Bangalore, India, pp. 393-398.

Publicador

IEEE

Relação

http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5401216

http://eprints.iisc.ernet.in/34071/

Palavras-Chave #Electronic Systems Engineering (Formerly, (CEDT) Centre for Electronic Design & Technology) #Supercomputer Education & Research Centre
Tipo

Conference Paper

PeerReviewed