V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Large-Signal Model for Independent DG MOSFET

In this paper, we show the limitations of the traditional charge linearization techniques for modeling terminal charges of the independent double-gate metal-oxide-semiconductor field-effect transistors. Based on our recent computationally efficient Poisson solution for independent double gate transistors, we propose a new charge linearization technique to model the terminal charges and transcapacitances. We report two different types of quasistatic large-signal models for the long-channel device. In the first type, the terminal charges are expressed as closed-form functions of the source- and drain-end inversion charge densities and found to be accurate when the potential distribution at source end of the channel is hyperbolic in nature. The second type, which is found to be accurate in all regimes of operations, is based on the quadratic spline collocation technique and requires the input voltage equation to be solved two more times, apart from the source and drain ends.

High On-Off Ratio Bilayer Graphene Complementary Field Effect Transistors

In this paper, we propose a novel S/D engineering for dual-gated Bilayer Graphene (BLG) Field Effect Transistor (FET) using doped semiconductors (with a bandgap) as source and drain to obtain unipolar complementary transistors. To simulate the device, a self-consistent Non-Equilibrium Green's Function (NEGF) solver has been developed and validated against published experimental data. Using the simulator, we predict an on-off ratio in excess of 10(4) and a subthreshold slope of similar to 110mV/decade with excellent scalability and current saturation, for a 20nm gate length unipolar BLG FET. However, the performance of the proposed device is found to be strongly dependent on the S/D series resistance effect. The obtained results show significant improvements over existing reports, marking an important step towards bilayer graphene logic devices.

Structural and electrical properties of radio frequency magnetron sputtered tantalum oxide films: Influence of post-deposition annealing

The as-deposited and annealed radio frequency reactive magnetron sputtered tantalum oxide (Ta2O5) films were characterized by studying the chemical binding configuration, structural and electrical properties. X-ray photoelectron spectroscopy and X-ray diffraction analysis of the films elucidate that the film annealed at 673 K was stoichiometric with orthorhombic beta-phase Ta2O5. The dielectric constant values of the tantalum oxide capacitors with the sandwich structure of Al/Ta2O5/Si were in the range from 14 to 26 depending on the post-deposition annealing temperature. The leakage current density was < 20 nA cm(-2) at the gate bias voltage of 0.04 MV/cm for the annealed films. The electrical conduction mechanism observed in the films was Poole-Frenkel. (C) 2010 Elsevier Ltd. All rights reserved.

Electrical and Optical Properties of Diketopyrrolopyrrole-Based Copolymer Interfaces in Thin Film Devices

Two donor acceptor diketopyrrolopyrrole (DPP)-based copolymers (PDPP-BBT and TDPP-BBT) have been synthesized for their application in organic devices such as metal-insulator semiconductor (MIS) diodes and field-effect transistors (FETs). The semiconductor-dielectric interface was characterized by capacitance-voltage and conductance-voltage methods. These measurements yield an interface trap density of 4.2 x 10(12) eV(-1) cm(-2) in TDPP-BBT and 3.5 x 10(12) eV(-1) cm(-2) in PDPP-BBT at the flat-band voltage. The FETs based on these spincoated DPP copolymers display p-channel behavior with hole mobilities of the order 10(-3) cm(2)/(V s). Light scattering studies from PDPP-BBT FETs show almost no change in the Raman spectrum after the devices are allowed to operate at a gate voltage, indicating that the FETs suffer minimal damage due to the metal-polymer contact or the application of an electric field. As a comparison Raman intensity profile from the channel-Au contact layer in pentacene FETs are presented, which show a distinct change before and after biasing.

An Efficient Robust Algorithm for the Surface-Potential Calculation of Independent DG MOSFET

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton-Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface.

Effect of Post-Metallization Hydrogen Annealing on C-V Characteristic of Zirconia Grown Using Atomic Layer Deposition

Substantial amount of fixed charge present in most of the alternative gate dielectrics gives rise to large shifts in the flat-band voltage (VFB) and charge trapping and de-trapping causes hysterectic changes on voltage cycling. Both phenomena affect stable and reliable transistor operation. In this paper we have studied for the first time the effect of post-metallization hydrogen annealing on the C-V curve of MOS capacitors employing zirconia, one of the most promising gate dielectric. Samples were annealed in hydrogen ambient for up to 30 minutes at different temperatures ranging from room temperature to 400°C. C-V measurements were done after annealing at each temperature and the hysteresis width was calculated from the C-V curves. A minimum hysteresis width of ∼35 mV was observed on annealing the sample at 200°C confirming the excellent suitability of this dielectric

Ellipsometry as a Sensitive Technique to Probe film -Substrate Interfaces: Al2O3 on Si(100)

An attempt has been made to study the film-substrate interface by using a sensitive, non- conventional tool. Because of the prospective use of gate oxide in MOSFET devices, we have chosen to study alumina films grown on silicon. Film-substrate interface of alumina grown by MOCVD on Si(100) was studied systematically using spectroscopic ellipsometry in the range 1.5-5.0 eV, supported by cross-sectional SEM, and SIMS. The (ε1,ε2) versus energy data obtained for films grown at 600°C, 700°C, and 750°C were modeled to fit a substrate/interface/film “sandwich”. The experimental results reveal (as may be expected) that the nature of the substrate -film interface depends strongly on the growth temperature. The simulated (ε1,ε2) patterns are in excellent agreement with observed ellipsometric data. The MOCVD precursors results the presence of carbon in the films. Theoretical simulation was able to account for the ellipsometry data by invoking the presence of “free” carbon in the alumina films.

Two-channel Kondo physics in odd impurity chains

We study odd-membered chains of spin-1/2 impurities, with each end connected to its own metallic lead. For antiferromagnetic exchange coupling, universal two-channel Kondo (2CK) physics is shown to arise at low energies. Two overscreening mechanisms are found to occur depending on coupling strength, with distinct signatures in physical properties. For strong interimpurity coupling, a residual chain spin-1/2 moment experiences a renormalized effective coupling to the leads, while in the weak-coupling regime, Kondo coupling is mediated via incipient single-channel Kondo singlet formation. We also investigate models in which the leads are tunnel-coupled to the impurity chain, permitting variable dot filling under applied gate voltages. Effective low-energy models for each regime of filling are derived, and for even fillings where the chain ground state is a spin singlet, an orbital 2CK effect is found to be operative. Provided mirror symmetry is preserved, 2CK physics is shown to be wholly robust to variable dot filling; in particular, the single-particle spectrum at the Fermi level, and hence the low-temperature zero-bias conductance, is always pinned to half-unitarity. We derive a Friedel-Luttinger sum rule and from it show that, in contrast to a Fermi liquid, the Luttinger integral is nonzero and determined solely by the ``excess'' dot charge as controlled by gate voltage. The relevance of the work to real quantum dot devices, where interlead charge-transfer processes fatal to 2CK physics are present, is also discussed. Physical arguments and numerical renormalization-group techniques are used to obtain a detailed understanding of these problems.

A Novel VSI- and CSI-Fed Dual Stator Induction Motor Drive Topology for Medium-Voltage Drive Applications

A new configuration is proposed for high-power induction motor drives. The induction machine is provided with two three-phase stator windings with their axes in line. One winding is designed for higher voltage and is meant to handle the main (active) power. The second winding is designed for lower voltage and is meant to carry the excitation (reactive) power. The excitation winding is powered by an insulated-gate-bipolar-transistor-based voltage source inverter with an output filter. The power winding is fed by a load-commutated current source inverter. The commutation of thyristors in the load-commutated inverter (LCI) is achieved by injecting the required leading reactive power from the excitation inverter. The MMF harmonics due to the LCI current are also cancelled out by injecting a suitable compensating component from the excitation inverter, so that the electromagnetic torque of the machine is smooth. Results from a prototype drive are presented to demonstrate the concept.

A low power, process invariant keeper design for high speed dynamic logic circuits

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130nm CMOS technology.

Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization

With extensive use of dynamic voltage scaling (DVS) there is increasing need for voltage scalable models. Similarly, leakage being very sensitive to temperature motivates the need for a temperature scalable model as well. We characterize standard cell libraries for statistical leakage analysis based on models for transistor stacks. Modeling stacks has the advantage of using a single model across many gates there by reducing the number of models that need to be characterized. Our experiments on 15 different gates show that we needed only 23 models to predict the leakage across 126 input vector combinations. We investigate the use of neural networks for the combined PVT model, for the stacks, which can capture the effect of inter die, intra gate variations, supply voltage(0.6-1.2 V) and temperature (0 - 100degC) on leakage. Results show that neural network based stack models can predict the PDF of leakage current across supply voltage and temperature accurately with the average error in mean being less than 2% and that in standard deviation being less than 5% across a range of voltage, temperature.

Unified Vdd Vth Optimization Based DVFM Controller for a Logic Block

In this paper analytical expressions for optimal Vdd and Vth to minimize energy for a given speed constraint are derived. These expressions are based on the EKV model for transistors and are valid in both strong inversion and sub threshold regions. The effect of gate leakage on the optimal Vdd and Vth is analyzed. A new gradient based algorithm for controlling Vdd and Vth based on delay and power monitoring results is proposed. A Vdd-Vth controller which uses the algorithm to dynamically control the supply and threshold voltage of a representative logic block (sum of absolute difference computation of an MPEG decoder) is designed. Simulation results using 65 nm predictive technology models are given.

Field emission properties of carbon nanotube arrays with defects and impurities

Field emission from carbon nanotubes (CNTs) in the form of arrays or thin films give rise to several strongly correlated process of electromechanical interaction and degradation. Such processes are mainly due to (1) electron-phonon interaction (2) electromechanical force field leading to stretching of CNTs (3) ballistic transport induced thermal spikes, coupled with high dynamic stress, leading to degradation of emission performance at the device scale. Fairly detailed physics based models of CNTs considering the aspects (1) and (2) above have already been developed by these authors, and numerical results indicate good agreement with experimental results. What is missing in such a system level modeling approach is the incorporation of structural defects and vacancies or charge impurities. This is a practical and important problem due to the fact that degradation of field emission performance is indeed observed in experimental I-V curves. What is not clear from these experiments is whether such degradation in the I-V response is due to dynamic reorientation of the CNTs or due to the defects or due to both of these effects combined. Non-equilibrium Green’s function based simulations using a tight-binding Hamiltonian for single CNT segment show up the localization of carrier density at various locations of the CNTs. About 11% decrease in the drive current with steady difference in the drain current in the range of 0.2-0.4V of the gate voltage was reported in literature when negative charge impurity was introduced at various locations of the CNT over a length of ~20nm. In the context of field emission from CNT tips, a simplistic estimate of defects have been introduced by a correction factor in the Fowler-Nordheim formulae. However, a more detailed physics based treatment is required, while at the same time the device-scale simulation is necessary. The novelty of our present approach is the following. We employ a concept of effective stiffness degradation for segments of CNTs, which is due to structural defects, and subsequently, we incorporate the vacancy defects and charge impurity effects in the Green’s function based approach. Field emission induced current-voltage characteristics of a vertically aligned CNT array on a Cu-Cr substrate is then simulated using a detailed nonlinear mechanistic model of CNTs coupled with quantum hydrodynamics. An array of 10 vertically aligned and each 12 m long CNTs is considered for the device scale analysis. Defect regions are introduced randomly over the CNT length. The result shows the decrease in the longitudinal strain due to defects. Contrary to the expected influence of purely mechanical degradation, this result indicates that the charge impurity and hence weaker transport can lead to a different electromechanical force field, which ultimately can reduce the strain. However, there could be significant fluctuation in such strain field due to electron-phonon coupling. The effect of such fluctuations (with defects) is clearly evident in the field emission current history. The average current also decreases significantly due to such defects.

Hardware implementation of 4x4 DCT/Quantization block using multiplication and error-free algorithm

The 4ÃÂ4 discrete cosine transform is one of the most important building blocks for the emerging video coding standard, viz. H.264. The conventional implementation does some approximation to the transform matrix elements to facilitate integer arithmetic, for which hardware is suitably prepared. Though the transform coding does not involve any multiplications, quantization process requires sixteen 16-bit multiplications. The algorithm used here eliminates the process of approximation in transform coding and multiplication in the quantization process, by usage of algebraic integer coding. We propose an area-efficient implementation of the transform and quantization blocks based on the algebraic integer coding. The designs were synthesized with 90 nm TSMC CMOS technology and were also implemented on a Xilinx FPGA. The gate counts and throughput achievable in this case are 7000 and 125 Msamples/sec.