A power-scalable RF CMOS receiver for 2.4 GHz Wireless Sensor Network applications

A power scalable receiver architecture is presented for low data rate Wireless Sensor Network (WSN) applications in 130nm RF-CMOS technology. Power scalable receiver is motivated by the ability to leverage lower run-time performance requirement to save power. The proposed receiver is able to switch power settings based on available signal and interference levels while maintaining requisite BER. The Low-IF receiver consists of Variable Noise and Linearity LNA, IQ Mixers, VGA, Variable Order Complex Bandpass Filter and Variable Gain and Bandwidth Amplifier (VGBWA) capable of driving variable sampling rate ADC. Various blocks have independent power scaling controls depending on their noise, gain and interference rejection (IR) requirements. The receiver is designed for constant envelope QPSK-type modulation with 2.4GHz RF input, 3MHz IF and 2MHz bandwidth. The chip operates at 1V Vdd with current scalable from 4.5mA to 1.3mA and chip area of 0.65mm2.

System-level SoC near-field (NF) emissions: Simulation to measurement correlation

As System-on-Chip (SoC) designs migrate to 28nm process node and beyond, the electromagnetic (EM) co-interactions of the Chip-Package-Printed Circuit Board (PCB) becomes critical and require accurate and efficient characterization and verification. In this paper a fast, scalable, and parallelized boundary element based integral EM solutions to Maxwell equations is presented. The accuracy of the full-wave formulation, for complete EM characterization, has been validated on both canonical structures and real-world 3-D system (viz. Chip + Package + PCB). Good correlation between numerical simulation and measurement has been achieved. A few examples of the applicability of the formulation to high speed digital and analog serial interfaces on a 45nm SoC are also presented.

Time-Based All-Digital Technique for Analog Built-in Self-Test

A scheme for built-in self-test of analog signals with minimal area overhead for measuring on-chip voltages in an all-digital manner is presented. The method is well suited for a distributed architecture, where the routing of analog signals over long paths is minimized. A clock is routed serially to the sampling heads placed at the nodes of analog test voltages. This sampling head present at each test node, which consists of a pair of delay cells and a pair of flip-flops, locally converts the test voltage to a skew between a pair of subsampled signals, thus giving rise to as many subsampled signal pairs as the number of nodes. To measure a certain analog voltage, the corresponding subsampled signal pair is fed to a delay measurement unit to measure the skew between this pair. The concept is validated by designing a test chip in a UMC 130-nm CMOS process. Sub-millivolt accuracy for static signals is demonstrated for a measurement time of a few seconds, and an effective number of bits of 5.29 is demonstrated for low-bandwidth signals in the absence of sample-and-hold circuitry.

Transcriptional Repression of Tumor Suppressor CDC73, Encoding an RNA Polymerase II Interactor, by Wilms Tumor 1 Protein (WT1) Promotes Cell Proliferation IMPLICATION FOR CANCER THERAPEUTICS

The Wilms tumor 1 gene (WT1) can either repress or induce the expression of genes. Inconsistent with its tumor suppressor role, elevated WT1 levels have been observed in leukemia and solid tumors. WT1 has also been suggested to act as an oncogene by inducing the expression of MYC and BCL-2. However, these are only the correlational studies, and no functional study has been performed to date. Consistent with its tumor suppressor role, CDC73 binds to RNA polymerase II as part of a PAF1 transcriptional regulatory complex and causes transcriptional repression of oncogenes MYC and CCND1. It also represses beta-catenin-mediated transcription. Based on the reduced level of CDC73 in oral squamous cell carcinoma (OSCC) samples in the absence of loss-of-heterozygosity, promoter methylation, and mutations, we speculated that an inhibitory transcription factor is regulating its expression. The bioinformatics analysis predicted WT1 as an inhibitory transcription factor to regulate the CDC73 level. Our results showed that overexpression of WT1 decreased CDC73 levels and promoted proliferation of OSCC cells. ChIP and EMSA results demonstrated binding of WT1 to the CDC73 promoter. The 5-azacytidine treatment of OSCC cells led to an up-regulation of WT1 with a concomitant down-regulation of CDC73, further suggesting regulation of CDC73 by WT1. Exogenous CDC73 attenuated the protumorigenic activity of WT1 by apoptosis induction. An inverse correlation between expression levels of CDC73 and WT1 was observed in OSCC samples. These observations indicated that WT1 functions as an oncogene by repressing the expression of CDC73 in OSCC. We suggest that targeting WT1 could be a therapeutic strategy for cancer, including OSCC.

Luminescent Molecular Sensors for Assessment of Temperature Field in Machining

A new technique based on luminescent molecular sensors is utilized in these series of experiments for measurement of temperatures in material removal processes. 2-Dimensional machining of metals at low speeds and surface grinding configurations are used as the model experimental systems to understand the efficacy of this experimental technique. The experiments were conducted with a series of luminescent sensors and binder combinations for the temperature measurement. The luminescence of the sensor was measured through a charge-coupled device imaging camera, and intensive calibration exercises were performed on these sensors. Excellent agreement in the temperature fields measured through this new experimental approach and traditional infrared thermography is seen here. This technique offers the unique capability of allowing measurement of temperatures in the presence of a lubricant, akin to manufacturing conditions in situ. Extension of the technique to measure the temperature field at the tool-chip contact is described.

Rad51-Rad52 Mediated Maintenance of Centromeric Chromatin in Candida albicans

Specification of the centromere location in most eukaryotes is not solely dependent on the DNA sequence. However, the non-genetic determinants of centromere identity are not clearly defined. While multiple mechanisms, individually or in concert, may specify centromeres epigenetically, most studies in this area are focused on a universal factor, a centromere-specific histone H3 variant CENP-A, often considered as the epigenetic determinant of centromere identity. In spite of variable timing of its loading at centromeres across species, a replication coupled early S phase deposition of CENP-A is found in most yeast centromeres. Centromeres are the earliest replicating chromosomal regions in a pathogenic budding yeast Candida albicans. Using a 2-dimensional agarose gel electrophoresis assay, we identify replication origins (ORI7-LI and ORI7-RI) proximal to an early replicating centromere (CEN7) in C. albicans. We show that the replication forks stall at CEN7 in a kinetochore dependent manner and fork stalling is reduced in the absence of the homologous recombination (HR) proteins Rad51 and Rad52. Deletion of ORI7-RI causes a significant reduction in the stalled fork signal and an increased loss rate of the altered chromosome 7. The HR proteins, Rad51 and Rad52, have been shown to play a role in fork restart. Confocal microscopy shows declustered kinetochores in rad51 and rad52 mutants, which are evidence of kinetochore disintegrity. CENP-A(CaCse4) levels at centromeres, as determined by chromatin immunoprecipitation (ChIP) experiments, are reduced in absence of Rad51/Rad52 resulting in disruption of the kinetochore structure. Moreover, western blot analysis reveals that delocalized CENP-A molecules in HR mutants degrade in a similar fashion as in other kinetochore mutants described before. Finally, co-immunoprecipitation assays indicate that Rad51 and Rad52 physically interact with CENP-A(CaCse4) in vivo. Thus, the HR proteins Rad51 and Rad52 epigenetically maintain centromere functioning by regulating CENP-A(CaCse4) levels at the programmed stall sites of early replicating centromeres.

Incipient straining in severe plastic deformation methods

Knowledge of the plasticity associated with the incipient stage of chip formation is useful toward developing an understanding of the deformation field underlying severe plastic deformation processes. The transition from a transient state of straining to a steady state was investigated in plane strain machining of a model material system-copper. Characterization of the evolution to a steady-state deformation field was made by image correlation, hardness mapping, load analysis, and microstructure characterization. Empirical relationships relating the deformation heterogeneity and the process parameters were found and explained by the corresponding effects on shear plane geometry. The results are potentially useful to facilitate a framework for process design of large strain deformation configurations, wherein transient deformation fields prevail. These implications are considered in the present study to quantify the efficiency of processing methods for bulk ultrafine-grained metals by large strain extrusion machining and equal channel angular pressing.

A MICROMACHINED WIDE-BAND IN-PLANE SINGLE-AXIS CAPACITIVE ACCELEROMETER WITH A DISPLACEMENT-AMPLIFYING COMPLIANT MECHANISM

With the premise that electronic noise dominates mechanical noise in micromachined accelerometers, we present here a method to enhance the sensitivity and resolution at kHz bandwidth using mechanical amplification. This is achieved by means of a Displacement-amplifying Compliant Mechanism (DaCM) that is appended to the usual sensing element comprising a proof-mass and a suspension. Differential comb-drive arrangement is used for capacitive-sensing. The DaCM is designed to match the stiffness of the suspension so that there is substantial net amplification without compromising the bandwidth. A spring-mass-lever model is used to estimate the lumped parameters of the system. A DaCM-aided accelerometer and another without a DaCM-both occupying the same footprint-are compared to show that the former gives enhanced sensitivity: 8.7 nm/g vs. 1.4 nm/g displacement at the sensing-combs under static conditions. A prototype of the DaCM-aided micromachined acclerometer was fabricated using bulk-micromachining. It was tested at the die-level and then packaged on a printed circuit board with an off-the-shelf integrated chip for measuring change in capacitance. Under dynamic conditions, the measured amplification factor at the output of the DaCM was observed to be about 11 times larger than the displacement of the proof-mass and thus validating the concept of enhancing the sensitivity of accelerometers using mechanical amplifiers. The measured first in-plane natural frequency of the fabricated accelerometer was 6.25 kHz. The packaged accelerometer with the DaCM was measured to have 26.7 mV/g sensitivity at 40 Hz.

Evidence that TSC2 acts as a transcription factor and binds to and represses the promoter of Epiregulin

The TSC2 gene, mutated in patients with tuberous sclerosis complex (TSC), encodes a 200 kDa protein TSC2 (tuberin). The importance of TSC2 in the regulation of cell growth and proliferation is irrefutable. TSC2 in complex with TSC1 negatively regulates the mTOR complex 1 (mTORC1) via RHEB in the PI3K-AKT-mTOR pathway and in turn regulates cell proliferation. It shows nuclear as well as cytoplasmic localization. However, its nuclear function remains elusive. In order to identify the nuclear function of TSC2, a whole-genome expression profiling of TSC2 overexpressing cells was performed, and the results showed differential regulation of 266 genes. Interestingly, transcription was found to be the most populated functional category. EREG (Epiregulin), a member of the epidermal growth factor family, was found to be the most downregulated gene in the microarray analysis. Previous reports have documented elevated levels of EREG in TSC lesions, making its regulatory aspects intriguing. Using the luciferase reporter, ChIP and EMSA techniques, we show that TSC2 binds to the EREG promoter between -352 bp and -303 bp and negatively regulates its expression. This is the first evidence for the role of TSC2 as a transcription factor and of TSC2 binding to the promoter of any gene.

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters

A logic gate-based digital frequency multiplication technique for low-power frequency synthesis is presented. The proposed digital edge combining approach offers broadband operation with low-power and low-area advantages and is a promising candidate for low-power frequency synthesis in deep submicrometer CMOS technologies. Chip prototype of the proposed frequency multiplication-based 2.4-GHz binary frequency-shift-keying (BFSK)/amplitude shift keying (ASK) transmitter (TX) was fabricated in 0.13-mu m CMOS technology. The TX achieves maximum data rates of 3 and 20 Mb/s for BFSK and ASK modulations, respectively, consuming a 14-mA current from 1.3 V supply voltage. The corresponding energy efficiencies of the TX are 3.6 nJ/bit for BFSK and 0.91 nJ/bit for ASK modulations.

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs

The charge-pump (CP) mismatch current is a dominant source of static phase error and reference spur in the nano-meter CMOS PLL implementations due to its worsened channel length modulation effect. This paper presents a charge-pump (CP) mismatch current reduction technique utilizing an adaptive body bias tuning of CP transistors and a zero CP mismatch current tracking PLL architecture for reference spur suppression. A chip prototype of the proposed circuit was implemented in 0.13 mu m CMOS technology. The frequency synthesizer consumes 8.2 mA current from a 13 V supply voltage and achieves a phase noise of -96.01 dBc/Hz @ 1 MHz offset from a 2.4 GHz RF carrier. The charge-pump measurements using the proposed calibration technique exhibited a mismatch current of less than 0.3 mu A (0.55%) over the VCO control voltage range of 0.3-1.0 V. The closed loop measurements show a minimized static phase error of within +/- 70 ps and a similar or equal to 9 dB reduction in reference spur level across the PLL output frequency range 2.4-2.5 GHz. The presented CP calibration technique compensates for the DC current mismatch and the mismatch due to channel length modulation effect and therefore improves the performance of CP-PLLs in nano-meter CMOS implementations. (C) 2015 Elsevier Ltd. All rights reserved.

Suspended core-shell Pt-PtOx nanostructure for ultrasensitive hydrogen gas sensor

High sensitivity gas sensors are typically realized using metal catalysts and nanostructured materials, utilizing non-conventional synthesis and processing techniques, incompatible with on-chip integration of sensor arrays. In this work, we report a new device architecture, suspended core-shell Pt-PtOx nanostructure that is fully CMOS-compatible. The device consists of a metal gate core, embedded within a partially suspended semiconductor shell with source and drain contacts in the anchored region. The reduced work function in suspended region, coupled with builtin electric field of metal-semiconductor junction, enables the modulation of drain current, due to room temperature Redox reactions on exposure to gas. The device architecture is validated using Pt-PtO2 suspended nanostructure for sensing H-2 down to 200 ppb under room temperature. By exploiting catalytic activity of PtO2, in conjunction with its p-type semiconducting behavior, we demonstrate about two orders of magnitude improvement in sensitivity and limit of detection, compared to the sensors reported in recent literature. Pt thin film, deposited on SiO2, is lithographically patterned and converted into suspended Pt-PtO2 sensor, in a single step isotropic SiO2 etching. An optimum design space for the sensor is elucidated with the initial Pt film thickness ranging between 10 nm and 30 nm, for low power (< 5 mu W), room temperature operation. (C) 2015 AIP Publishing LLC.

Router Attack toward NoC-enabled MPSoC and Monitoring Countermeasures against such Threat

The growing number of applications and processing units in modern Multiprocessor Systems-on-Chips (MPSoCs) come along with reduced time to market. Different IP cores can come from different vendors, and their trust levels are also different, but typically they use Network-on-Chip (NoC) as their communication infrastructure. An MPSoC can have multiple Trusted Execution Environments (TEEs). Apart from performance, power, and area research in the field of MPSoC, robust and secure system design is also gaining importance in the research community. To build a secure system, the designer must know beforehand all kinds of attack possibilities for the respective system (MPSoC). In this paper we survey the possible attack scenarios on present-day MPSoCs and investigate a new attack scenario, i.e., router attack targeted toward NoC architecture. We show the validity of this attack by analyzing different present-day NoC architectures and show that they are all vulnerable to this type of attack. By launching a router attack, an attacker can control the whole chip very easily, which makes it a very serious issue. Both routing tables and routing logic-based routers are vulnerable to such attacks. In this paper, we address attacks on routing tables. We propose different monitoring-based countermeasures against routing table-based router attack in an MPSoC having multiple TEEs. Synthesis results show that proposed countermeasures, viz. Runtime-monitor, Restart-monitor, Intermediate manager, and Auditor, occupy areas that are 26.6, 22, 0.2, and 12.2 % of a routing table-based router area. Apart from these, we propose Ejection address checker and Local monitoring module inside a router that cause 3.4 and 10.6 % increase of a router area, respectively. Simulation results are also given, which shows effectiveness of proposed monitoring-based countermeasures.

Co-Exploration of NLA Kernels and Specification of Compute Elements in Distributed Memory CGRAs

Coarse Grained Reconfigurable Architectures (CGRA) are emerging as embedded application processing units in computing platforms for Exascale computing. Such CGRAs are distributed memory multi- core compute elements on a chip that communicate over a Network-on-chip (NoC). Numerical Linear Algebra (NLA) kernels are key to several high performance computing applications. In this paper we propose a systematic methodology to obtain the specification of Compute Elements (CE) for such CGRAs. We analyze block Matrix Multiplication and block LU Decomposition algorithms in the context of a CGRA, and obtain theoretical bounds on communication requirements, and memory sizes for a CE. Support for high performance custom computations common to NLA kernels are met through custom function units (CFUs) in the CEs. We present results to justify the merits of such CFUs.

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.