A Systematic Approach to Synthesis of Verification Test-suites for Modular SoC Designs

Verification is one of the important stages in designing an SoC (system on chips) that consumes upto 70% of the design time. In this work, we present a methodology to automatically generate verification test-cases to verify a class of SoCs and also enable re-use of verification resources created from one SoC to another. A prototype implementation for generating the test-cases is also presented.

Scan cell reordering to minimize peak power during test cycle: A graph theoretic approach

Scan circuit is widely practiced DFT technology. The scan testing procedure consist of state initialization, test application, response capture and observation process. During the state initialization process the scan vectors are shifted into the scan cells and simultaneously the responses captured in last cycle are shifted out. During this shift operation the transitions that arise in the scan cells are propagated to the combinational circuit, which inturn create many more toggling activities in the combinational block and hence increases the dynamic power consumption. The dynamic power consumed during scan shift operation is much more higher than that of normal mode operation.

A Fast Linear Separability Test by Projection of Positive Points on Subspaces

A geometric and non parametric procedure for testing if two finite set of points are linearly separable is proposed. The Linear Separability Test is equivalent to a test that determines if a strictly positive point h > 0 exists in the range of a matrix A (related to the points in the two finite sets). The algorithm proposed in the paper iteratively checks if a strictly positive point exists in a subspace by projecting a strictly positive vector with equal co-ordinates (p), on the subspace. At the end of each iteration, the subspace is reduced to a lower dimensional subspace. The test is completed within r ≤ min(n, d + 1) steps, for both linearly separable and non separable problems (r is the rank of A, n is the number of points and d is the dimension of the space containing the points). The worst case time complexity of the algorithm is O(nr3) and space complexity of the algorithm is O(nd). A small review of some of the prominent algorithms and their time complexities is included. The worst case computational complexity of our algorithm is lower than the worst case computational complexity of Simplex, Perceptron, Support Vector Machine and Convex Hull Algorithms, if d

Analog/RF Built-in-Self-Test Subsystem for a Mobile Broadcast Video Receiver in 65-nm CMOS

A built-in-self-test (BIST) subsystem embedded in a 65-nm mobile broadcast video receiver is described. The subsystem is designed to perform analog and RF measurements at multiple internal nodes of the receiver. It uses a distributed network of CMOS sensors and a low bandwidth, 12-bit A/D converter to perform the measurements with a serial bus interface enabling a digital transfer of measured data to automatic test equipment (ATE). A perturbation/correlation based BIST method is described, which makes pass/fail determination on parts, resulting in significant test time and cost reduction.

A mostly-digital analog scan-out chain for low bandwidth voltage measurement for analog IP test

A method of precise measurement of on-chip analog voltages in a mostly-digital manner, with minimal overhead, is presented. A pair of clock signals is routed to the node of an analog voltage. This analog voltage controls the delay between this pair of clock signals, which is then measured in an all-digital manner using the technique of sub-sampling. This sub-sampling technique, having measurement time and accuracy trade-off, is well suited for low bandwidth signals. This concept is validated by designing delay cells, using current starved inverters in UMC 130nm CMOS process. Sub-mV accuracy is demonstrated for a measurement time of few seconds.

Fabrication of corrosion resistant, bioactive and antibacterial silver substituted hydroxyapatite/titania composite coating on Cp Ti

The present work is aimed at developing a bioactive, corrosion resistant and anti bacterial nanostructured silver substituted hydroxyapatite/titania (AgHA/TiO(2)) composite coating in a single step on commercially pure titanium (Cp Ti) by plasma electrolytic processing (PEP) technique. For this purpose 2.5 wt% silver substituted hydroxyapatite (AgHA) nanoparticles were prepared by microwave processing technique and were characterized by X-ray diffraction (XRD), Fourier-transform infrared (FT-IR) spectroscopy and transmission electron microscopy (TEM) methods. The as-synthesized AgHA particles with particle length ranging from 60 to 70 nm and width ranging from 15 to 20 nm were used for the subsequent development of coating on Cp Ti. The PEP treated Cp Ti showed both titania and AgHA in its coating and exhibited an improved corrosion resistance in 7.4 pH simulated body fluid (SBF) and 4.5 pH osteoclast bioresorbable conditions compared to untreated Cp Ti. The in vitro bioactivity test conducted under Kokubo SBF conditions indicated an enhanced apatite forming ability of PEP treated Cp Ti surface compared to that of the untreated Cp Ti. The Kirby-Bauer disc diffusion method or antibiotic sensitivity test conducted with the test organisms of Escherichia coli (E. coli) for 24 h showed a significant zone of inhibition for PEP treated Cp Ti compared to untreated Cp Ti. (C) 2011 Elsevier Ltd and Techna Group S.r.l. All rights reserved.