Analysis of transients in a canal network

A generalised formulation of the mathematical model developed for the analysis of transients in a canal network, under subcritical flow, with any realistic combination of control structures and their multiple operations, has been presented. The model accounts for a large variety of control structures such as weirs, gates, notches etc. discharging under different conditions, namely submerged and unsubmerged. A numerical scheme to compute and approximate steady state flow condition as the initial condition has also been presented. The model can handle complex situations that may arise from multiple gate operations. This has been demonstrated with a problem wherein the boundary conditions change from a gate discharge equation to an energy equation and back to a gate discharge equation. In such a situation the wave strikes a fixed gate and leads to large and rapid fluctuations in both discharge and depth.

Effect of a linear potential variation on the gate of an FET

This correspondence aims at reporting the results of an analysis carried out to find the effect of a linear potential variation on the gate of an FET.

Effects of Parasitics and Interface Traps on Ballistic Nanowire FET in the Ultimate Quantum Capacitance Limit

In this paper, we focus on the performance of a nanowire field-effect transistor in the ultimate quantum capacitance limit (UQCL) (where only one subband is occupied) in the presence of interface traps (D-it), parasitic capacitance (C-L), and source/drain series resistance (R-s,R-d), using a ballistic transport model and compare the performance with its classical capacitance limit (CCL) counterpart. We discuss four different aspects relevant to the present scenario, namely: 1) gate capacitance; 2) drain-current saturation; 3) subthreshold slope; and 4) scaling performance. To gain physical insights into these effects, we also develop a set of semianalytical equations. The key observations are as follows: 1) A strongly energy-quantized nanowire shows nonmonotonic multiple-peak C-V characteristics due to discrete contributions from individual subbands; 2) the ballistic drain current saturates better in the UQCL than in the CCL, both in the presence and absence of D-it and R-s,R-d; 3) the subthreshold slope does not suffer any relative degradation in the UQCL compared to the CCL, even with Dit and R-s,R-d; 4) the UQCL scaling outperforms the CCL in the ideal condition; and 5) the UQCL scaling is more immune to R-s,R-d, but the presence of D-it and C-L significantly degrades the scaling advantages in the UQCL.

A Simulation Based Study and Analysis of Double Gate Tunnel FET Performance for Low Stand-By Power Applications

The conventional metal oxide semiconductor field effect transistor (MOSFET)may not be suitable for future low standby power (LSTP) applications due to its high off-state current as the sub-threshold swing is theoretically limited to 60mV/decade. Tunnel field effect transistor (TFET) based on gate controlled band to band tunneling has attracted attention for such applications due to its extremely small sub-threshold swing (much less than 60mV/decade). This paper takes a simulation approach to gain some insight into its electrostatics and the carrier transport mechanism. Using 2D device simulations, a thorough study and analysis of the electrical parameters of the planar double gate TFET is performed. Due to excellent sub-threshold characteristics and a reverse biased structure, it offers orders of magnitude less leakage current compared to the conventional MOSFET. In this work, it is shown that the device can be scaled down to channel lengths as small as 30 nm without affecting its performance. Also, it is observed that the bulk region of the device plays a major role in determining the sub-threshold characteristics of the device and considerable improvement in performance (in terms of ION/IOFF ratio) can be achieved if the thickness of the device is reduced. An ION/IOFF ratio of 2x1012 and a minimum point sub-threshold swing of 22mV/decade is obtained.

Design of a high sensitivity FET integrated MEMS microphone

FET based MEMS microphones comprise of a flexible diaphragm that works as the moving gate of the transistor. The integrated electromechanical transducer can be made more sensitive to external sound pressure either by increasing the mechanical or the electrical sensitivities. We propose a method of increasing the overall sensitivity of the microphone by increasing its electrical sensitivity. The proposed microphone uses the transistor biased in the sub-threshold region where the drain current depends exponentially on the difference between the gate-to-source voltage and the threshold voltage. The device is made more sensitive without adding any complexity in the mechanical design of the diaphragm.

A Computationally Efficient Generalized Poisson Solution for Independent Double-Gate Transistors

Previous techniques used for solving the 1-D Poisson equation ( PE) rigorously for long-channel asymmetric and independent double-gate (IDG) transistors result in potential models that involve multiple intercoupled implicit equations. As these equations need to be solved self-consistently, such potential models are clearly inefficient for compact modeling. This paper reports a different rigorous technique for solving the same PE by which one can obtain the potential profile of a generalized IDG transistor that involves a single implicit equation. The proposed Poisson solution is shown to be computationally more efficient for circuit simulation than the previous solutions.

HFinFET: A Scalable, High Performance, Low Leakage Hybrid n-Channel FET

In this letter, we propose the design and simulation study of a novel transistor, called HFinFET, which is a hybrid of an HEMT and a FinFET, to obtain excellent performance and good OFF-state control. Followed by the description of the design, 3-D device simulation has been performed to predict the characteristics of the device. The device has been benchmarked against published state of the art HEMT as well as planar and nonplanar Si n-MOSFET data of comparable gate length using standard benchmarking techniques.

Threshold voltage model for accumulation mode polycrystalline SOI MOSFETs and comparisons with experimental results

In this paper, a simple but accurate semi analytical charge sheet model is presented for threshold voltage of accumulation mode polycrystalline silicon on insulator (PSOI) MOSFETs. In this model, we define the threshold voltage (V-T) of the polysilicon accumulation mode MOSFET as the gate voltage required to raise the surface potential (phi(s)) to a value phi(sT) necessary to overcome the charge trapping in the grain boundary and to create channel accumulation charge that is equal to the channel accumulation charge available in the case of single crystal silicon accumulation mode MOSFET at that phi(sT). The correctness of the model is demonstrated by comparing the theoretically estimated values of threshold voltage with the experimentally measured threshold voltages on the accumulation mode PSOI MOSFETs fabricated in the laboratory using LPCVD polysilicon layers doped with boron to achieve dopant densities in the range 3.3 x 10(-15)-5 x 10(17)/cm(3). Further, it is shown that the threshold voltage values of accumulation mode PSOI MOSFETs predicted by the present model match very closely with the experimental results, better than those obtained with the models previously reported in the literature. (C) 2012 Elsevier B.V. All rights reserved.

Proposal for Graphene-Boron Nitride Heterobilayer-Based Tunnel FET

We investigate the gate-controlled direct band-to-band tunneling (BTBT) current in a graphene-boron nitride (G-BN) heterobilayer channel-based tunnel field effect transistor. We first study the imaginary band structure of hexagonal and Bernal-stacked heterobilayers by density functional theory, which is then used to evaluate the gate-controlled current under the Wentzel-Kramers-Brillouin approximation. It is shown that the direct BTBT is probable for a certain interlayer spacing of the G-BN which depends on the stacking orders.

Fin-Enabled-Area-Scaled Tunnel FET

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, 15x reduction in the OFF-current, 3x increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly 6x reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements.

Modeling of Channel Potential and Subthreshold Slope of Symmetric Double-Gate Transistor

A new physically based classical continuous potential distribution model, particularly considering the channel center, is proposed for a short-channel undoped body symmetrical double-gate transistor. It involves a novel technique for solving the 2-D nonlinear Poisson's equation in a rectangular coordinate system, which makes the model valid from weak to strong inversion regimes and from the channel center to the surface. We demonstrated, using the proposed model, that the channel potential versus gate voltage characteristics for the devices having equal channel lengths but different thicknesses pass through a single common point (termed ``crossover point''). Based on the potential model, a new compact model for the subthreshold swing is formulated. It is shown that for the devices having very high short-channel effects (SCE), the effective subthreshold slope factor is mainly dictated by the potential close to the channel center rather than the surface. SCEs and drain-induced barrier lowering are also assessed using the proposed model and validated against a professional numerical device simulator.

Within-Die Gate Delay Variability Measurement using Re-configurable Ring Oscillator

We report a circuit technique to measure the on-chip delay of an individual logic gate (both inverting and non-inverting) in its unmodified form using digitally reconfigurable ring oscillator (RO). Solving a system of linear equations with different configuration setting of the RO gives delay of an individual gate. Experimental results from a test chip in 65nm process node show the feasibility of measuring the delay of an individual inverter to within 1pS accuracy. Delay measurements of different nominally identical inverters in close physical proximity show variations of up to 26% indicating the large impact of local or within-die variations.

Stochastic differential games with multiple modes

We have studied two person stochastic differential games with multiple modes. For the zero-sum game we have established the existence of optimal strategies for both players. For the nonzero-sum case we have proved the existence of a Nash equilibrium.

Design of multi-frequency microstrip antennas using multiple rings

An electromagnetically coupled feed arrangement is proposed for simultaneously exciting multiple concentric ring antennas for multi-frequency operation. This has a multi-layer dielectric configuration in which a transmission line is embedded below the layer containing radiating rings. Energy coupled to these rings from the line beneath is optimised by suitably adjusting the location and dimensions of stubs on the line. It has been shown that the resonant frequencies of these rings do not change as several of these single-frequency antennas are combined to form a multi-resonant antenna. Furthermore, all radiators are forced to operate at their primary mode and some harmonics of the lower resonant frequency rings appearing within the frequency range are suppressed when combined. The experimental prototype antenna has three resonant frequencies at which it has good radiation characteristics.

Detection of the protein dimers, multiple monomeric states and hydrated forms of Plasmodium falciparum triosephosphate isomerase in the gas phase

Dimeric and monomeric forms of the enzyme triosephosphate isomerase (TIM) from Plasmodium falciparum (Pf) have been detected under conditions of nanoflow by electrospray mass spectrometry. The dimer (M = 55 663 Da) exhibits a narrow charge state distribution with intense peaks limited to values of 18(+) to 21(+), maximal intensity being observed for charge states 19(+) and 20(+). A monomeric species with a charge state distribution ranging from 11(+) to 16(+) is also observed, which may be assigned to folded dissociated subunits. Complete dimer dissociation results under normal electrospray condition. The effects of solution pH and source temperature have been investigated. The observation of four distinct charge state distributions which may be assigned to a dimer, folded monomer, partially folded monomer and unfolded monomer is reported. Circular dichromism and fluorescence studies of Pf TIM at low pH support the retention of substantial secondary and tertiary structures. Satellite peaks in mass spectra corresponding to hydrated species are also observed and isotope shift upon deuteration is demonstrated. The analysis of all available independent crystal structures of Pf TIM and TIMs from other organisms permits identification of structurally conserved water molecules. Hydration observed in the dimer and folded monomeric forms in the gas phase may correspond to these conserved sites.