A 1,000 Frames/s Programmable Vision Chip with Variable Resolution and Row-Pixel-Mixed Parallel Image Processors

A programmable vision chip with variable resolution and row-pixel-mixed parallel image processors is presented. The chip consists of a CMOS sensor array, with row-parallel 6-bit Algorithmic ADCs, row-parallel gray-scale image processors, pixel-parallel SIMD Processing Element (PE) array, and instruction controller. The resolution of the image in the chip is variable: high resolution for a focused area and low resolution for general view. It implements gray-scale and binary mathematical morphology algorithms in series to carry out low-level and mid-level image processing and sends out features of the image for various applications. It can perform image processing at over 1,000 frames/s (fps). A prototype chip with 64 x 64 pixels resolution and 6-bit gray-scale image is fabricated in 0.18 mu m Standard CMOS process. The area size of chip is 1.5 mm x 3.5 mm. Each pixel size is 9.5 mu m x 9.5 mu m and each processing element size is 23 mu m x 29 mu m. The experiment results demonstrate that the chip can perform low-level and mid-level image processing and it can be applied in the real-time vision applications, such as high speed target tracking.

A Novel CMOS Color Pixel for Vision Chips

This paper presents a novel CMOS color pixel with a 2D metal-grating structure for real-time vision chips. It consists of an N-well/P-substrate diode without salicide and 2D metal-grating layers on the diode. The periods of the 2D metal structure are controlled to realize color filtering. We implemented sixteen kinds of the pixels with the different metal-grating structures in a standard 0.18 mu m CMOS process. The measured results demonstrate that the N-well/P-substrate diode without salicide and with the 2D metal-grating structures can serve as the high speed RGB color active pixel sensor for real-time vision chips well.

Fabrication of an integrated pixel with an organic light-emitting diode driven by copper phthalocyanine organic thin film transistors

An organic integrated pixel with organic light-emitting diodes (OLEDs) driven by organic thin film transistors (OTFTs) is fabricated by a greatly simplified processing. The OTFTs are based on copper phthalocyanine as the active medium and fabricated on indium-tin-oxide (ITO) glass with top-gate structure, thus an organic integrated pixel is easily made by integrating OLED with OTFT. The OTFTs show field-effect mobility of 0.4 cm(2) /Vs and on/off ratio of 10(3) order. The OLED is driven well and emits the brightness as large as 2100cd/m(2) at a current density of 14.6 mu A/cm(2) at -19.7 V gate voltage. This simple device structure is promising in the future large-area flexible OLED displays.

Compact parallel optical modified-signed-digit arithmetic-logic array processor with electron-trapping device

A compact two-step modified-signed-digit arithmetic-logic array processor is proposed. When the reference digits are programmed, both addition and subtraction can be performed by the same binary logic operations regardless of the sign of the input digits. The optical implementation and experimental demonstration with an electron-trapping device are shown. Each digit is encoded by a single pixel, and no polarization is included. Any combinational logic can be easily performed without optoelectronic and electro-optic conversions of the intermediate results. The system is compact, general purpose, simple to align, and has a high signal-to-noise ratio. (C) 1999 Optical Society of America.

Parallel optical negabinary signed-digit computing: algorithm and optical implementation

Negabinary is a component of the positional number system. A complete set of negabinary arithmetic operations are presented, including the basic addition/subtraction logic, the two-step carry-free addition/subtraction algorithm based on negabinary signed-digit (NSD) representation, parallel multiplication, and the fast conversion from NSD to the normal negabinary in the carry-look-ahead mode. All the arithmetic operations can be performed with binary logic. By programming the binary reference bits, addition and subtraction can be realized in parallel with the same binary logic functions. This offers a technique to perform space-variant arithmetic-logic functions with space-invariant instructions. Multiplication can be performed in the tree structure and it is simpler than the modified signed-digit (MSD) counterpart. The parallelism of the algorithms is very suitable for optical implementation. Correspondingly, a general-purpose optical logic system using an electron trapping device is suggested. Various complex logic functions can be performed by programming the illumination of the data arrays without additional temporal latency of the intermediate results. The system can be compact. These properties make the proposed negabinary arithmetic-logic system a strong candidate for future applications in digital optical computing with the development of smart pixel arrays. (C) 1999 Society of Photo-Optical Instrumentation Engineers. [S0091-3286(99)00803-X].

A high accuracy image sensor for sinusoidal phase-modulating interferometry

We proposed a high accuracy image sensor technique for sinusoidal phase-modulating interferometer in the field of the surface profile measurements. It solved the problem of the CCD's pixel offset of the same column under two adjacent rows, eliminated the spectral leakage, and reduced the influence of external interference to the measurement accuracy. We measured the surface profile of a glass plate, and its repeatability precision was less than 8 nm and its relative error was 1.15 %. The results show that it can be used to measure surface profile with high accuracy and strong anti-interference ability. (C) 2007 Elsevier GmbH. All rights reserved.

Algorithm of far-field centre estimation based on phase-only matched filter

Estimation of the far-field centre is carried out in beam auto-alignment. In this paper, the features of the far-field of a square beam are presented. Based on these features, a phase-only matched filter is designed, and the algorithm of centre estimation is developed. Using the simulated images with different kinds of noise and the 40 test images that are taken in sequence, the accuracy of this algorithm is estimated. Results show that the error is no more than one pixel for simulated noise images with a 99% probability, and the stability is restricted within one pixel for test images. Using the improved algorithm, the consumed time is reduced to 0.049 s.

Growth and Characterization of GaSb-Based Type-II InAs/GaSb Superlattice Photodiodes for Mid-Infrared Detection

InAs/GaSb superlattice (SL) midwave infrared photovoltaic detectors are grown by molecular beam epitaxy on GaSb(001) residual p-type substrates. A thick GaSb layer is grown under the optimized growth condition as a buffer layer. The detectors containing a 320-period 8ML/8ML InAs/GaSb SL active layer are fabricated with a series pixel area using anode sulfide passivation. Corresponding to 50% cutoff wavelengths of 5.0 mu m at 77 K, the peak directivity of the detectors is 1.6 x 10(10) cm.Hz(1/2) W-1 at 77 K.

A programmable SIMD vision chip for real-time vision applications

A programmable vision chip for real-time vision applications is presented. The chip architecture is a combination of a SIMD processing element array and row-parallel processors, which can perform pixel-parallel and row-parallel operations at high speed. It implements the mathematical morphology method to carry out low-level and mid-level image processing and sends out image features for high-level image processing without I/O bottleneck. The chip can perform many algorithms through software control. The simulated maximum frequency of the vision chip is 300 MHz with 16 x 16 pixels resolution. It achieves the rate of 1000 frames per second in real-time vision. A prototype chip with a 16 x 16 PE array is fabricated by the 0.18 mu m standard CMOS process. It has a pixel size of 30 mu m x 40 mu m and 8.72 mW power consumption with a 1.8 V power supply. Experiments including the mathematical morphology method and target tracking application demonstrated that the chip is fully functional and can be applied in real-time vision applications.

GaAs Based InAs/GaSb Superlattice Short Wavelength Infrared Detectors Grown by Molecular Beam Epitaxy

InAs/GaSb superlattice (SL) short wavelength infrared photoconduction detectors are grown by molecular beam epitaxy on GaAs(001) semi-insulating substrates. An interfacial misfit mode AlSb quantum dot layer and a thick GaSb layer are grown as buffer layers. The detectors containing a 200-period 2ML/8ML InAs/GaSb SL active layer are fabricated with a pixel area of 800 x 800 mu m(2) without using passivation or antireflection coatings. Corresponding to the 50% cutoff wavelengths of 2.05 mu m at 77K and 2.25 mu m at 300 K, the peak detectivities of the detectors are 4 x 10(9) cm.Hz(1/2)/W at 77K and 2 x 10(8) cm.Hz(1/2)/W at 300 K, respectively.

High resolution interrogation technique based on linear photodiode array spectrometer for fiber Bragg grating Sensors - art. no. 65952C

A linear photodiode array spectrometer based, high resolution interrogation technique for fiber Bragg grating sensors is demonstrated. Spline interpolation and Polynomial Approximation Algorithm (PAA) are applied to the data points acquired by the spectrometer to improve the original PAA based interrogation method. Thereby fewer pixels are required to achieve the same resolution as original. Theoretical analysis indicates that if the FWHM of a FBG covers more than 3 pixels, the resolution of central wavelength shift will arrive at less than 1 pm. While the number of pixels increases to 6, the nominal resolution will decrease to 0.001 pm. Experimental result shows that Bragg wavelength resolution of similar to 1 pm is obtained for a FBG with FWHM of similar to 0.2 nm using a spectrometer with a pixel resolution of similar to 70 pm.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

Quantum well infrared photodetector simultaneously working in two atmospheric windows

We have demonstrated a two-contact quantum well infrared photodetector (QWIP) exhibiting simultaneous photoresponse in both the mid- and the long-wavelength atmospheric windows of 3-5 mu m and of 8-12 mu m. The structure of the device was achieved by sequentially growing a mid-wavelength QWIP part followed by a long-wavelength QWIP part separated by an n-doped layer. Compared with the conventional dual-band QWIP device utilizing three ohmic contacts, our QWIP is promising to greatly facilitate two-color focal plane array (FPA) fabrication by reducing the number of the indium bumps per pixel from three to one just like a monochromatic FPA fabrication and to increase the FPA fill factor by reducing one contact per pixel; another advantage may be that this QWIP FPA boasts broadband detection capability in the two atmospheric windows while using only a monochromatic readout integrated circuit. We attributed this simultaneous broadband detection to the different distributions of the total bias voltage between the mid- and long-wavelength QWIP parts.