Analog-digital and digital-analog converters using single-electron and MOS transistors

This paper proposes two kinds of novel single-electron analog-digital conversion (ADC) and digital-analog conversion (DAC) circuits that consist of single-electron transistors (SETs) and metal-oxide-semiconductor (MOS) transistors. The SET/MOS hybrid ADC and DAC circuits possess the merits of the SET circuit and the MOS circuit. We obtain the SPICE macro-modeling code of the SET transistor by studying and fitting the characteristics of the SET with SPICE simulation and Monte Carlo simulation methods. The SPICE macro-modeling code is used for the simulation of the SET/MOS hybrid ADC and DAC circuits. We simulate the performances of the SET/MOS hybrid 3-b ADC and 2-b DAC circuits by using the H-SPICE simulator. The simulation results demonstrate that the hybrid circuits can perform analog-digital and digital-analog data conversion well at room temperature. The hybrid ADC and DAC circuits have advantages as-follows: 1) compared with conventional circuits, the architectures of the circuits are simpler; 2) compared with single electron transistor circuits, the circuits have much larger load capability; 3) the power dissipation of the circuits are lower than uW; 4) the data conversion rate of the circuits can exceed 100 MHz; and 5) the resolution of the ADC and DAC circuits can be increased by the pipeline architectures.

Comparison of field effect transistor characteristics between space-grown and earth-grown gallium arsenide single crystal substrates

Semi-insulating gallium arsenide single crystal grown in space has been used in fabricating low noise field effect transistors and analog switch integrated circuits by the direct ion-implantation technique. All key electrical properties of these transistors and integrated circuits have surpassed those made from conventional earth-grown gallium arsenide. This result shows that device-grade space-grown semiconducting single crystal has surpassed the best terrestrial counterparts. (C) 2001 American Institute of Physics.

Application of sample-and-hold circuits in the laser frequency-shifting

A new method of frequency-shifting for a diode laser is realized. Using a sample-and-hold circuit, the error signal can be held by the circuit during frequency shifting. It can avoid the restraint of locking or even lock-losing caused by the servo circuit when we input a step-up voltage into piezoelectric transition (PZT) to achieve laser frequency-shifting.

Disconnection of the hippocampal-prefrontal cortical circuits impairs spatial working memory performance in rats

There is a unidirectional, ipsilateral and monosynaptic projection from the hippocampus to the prefrontal cortex. The cognitive function of hippocampal-prefrontal cortical circuit is not well established. In this paper, we use muscimol treated rats to inv

Fabrication and characterization of active and sequential circuits utilizing Schottky-wrap-gate-controlled GaAs hexagonal nanowire network structures

For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.

Influence of V/III ratio on the structural and photoluminescence properties of In0.52AlAs/In0.53GaAs metamorphic high electron mobility transistor grown by molecular beam epitaxy

A series of metamorphic high electron mobility transistors (MMHEMTs) with different V/III flux ratios are grown on GaAs (001) substrates by molecular beam epitaxy (XIBE). The samples are analysed by using atomic force microscopy (AFM), Hall measurement, and low temperature photoluminescence (PL). The optimum V/III ratio in a range from 15 to 60 for the growth of MMHEMTs is found to be around 40. At this ratio, the root mean square (RMS) roughness of the material is only 2.02 nm; a room-temperature mobility and a sheet electron density are obtained to be 10610.0cm(2)/(V.s) and 3.26 x 10(12)cm(-2) respectively. These results are equivalent to those obtained for the same structure grown on InP substrate. There are two peaks in the PL spectrum of the structure, corresponding to two sub-energy levels of the In0.53Ga0.47 As quantum well. It is found that the photoluminescence intensities of the two peaks vary with the V/III ratio, for which the reasons are discussed.

A new phototransistor with uni-travelling-carrier and optically gradual coupling properties

Based on appropriate combination of different band-gap InGaAsP, a new edge-coupled two-terminal double heterojunction phototransistor (ECTT-DHPT) was designed and fabricated, which is double heterojunction, free-aluminium, and works under uni-travelling-carrier mode and optically gradual coupling mode. This device is fully compatible with monolithic micro-wave integrated circuits (MMIC) and heterojunction bipolar transistor (HBT) in material and process. The DC characteristics reveal that the new ECTT-DHPT can perform good optoelectronic mix operation and linear amplification operation by optically biased at two appropriate value respectively. Responsivity of more than 52 A/W and dark current of 70 nA (when V-EC = 1 V) were obtained.

Properties of AlyGa1-yN/AlxGa1-xN/AlN/GaN Double-Barrier High Electron Mobility Transistor Structure

Electrical properties of AlyGa1-yN/AlxGa1-xN/AlN/GaN structure are investigated by solving coupled Schrodinger and Poisson equation self-consistently. Our calculations show that the two-dimensional electron gas (2DEG) density will decrease with the thickness of the second barrier (AlyGa1-yN) once the AlN content of the second barrier is smaller than a critical value y(c), and will increase with the thickness of the second barrier (AlyGa1-yN) when the critical AlN content of the second barrier y(c) is exceeded. Our calculations also show that the critical AlN content of the second barrier y(c) will increase with the AlN content and the thickness of the first barrier layer (AlxGa1-xN).

Whispering-gallery microcavity semiconductor lasers suitable for photonic integrated circuits and optical interconnects

The characteristics of whispering-gallery-like modes in the equilateral triangle and square microresonators are introduced, including directional emission triangle and square microlasers connected to an output waveguide. We propose a photonic interconnect scheme by connecting two directional emission microlasers with an optical waveguide on silicon integrated circuit chip. The measurement indicates that the triangle microlasers can work as a resonance enhanced photodetector for optical interconnect.

Quantum mechanical simulation of nanosized metal-oxide-semiconductor field-effect transistor using empirical pseudopotentials: A comparison for charge density occupation methods

The atomistic pseudopotential quantum mechanical calculations are used to study the transport in million atom nanosized metal-oxide-semiconductor field-effect transistors. In the charge self-consistent calculation, the quantum mechanical eigenstates of closed systems instead of scattering states of open systems are calculated. The question of how to use these eigenstates to simulate a nonequilibrium system, and how to calculate the electric currents, is addressed. Two methods to occupy the electron eigenstates to yield the charge density in a nonequilibrium condition are tested and compared. One is a partition method and another is a quasi-Fermi level method. Two methods are also used to evaluate the current: one uses the ballistic and tunneling current approximation, another uses the drift-diffusion method. (C) 2009 American Institute of Physics. [doi:10.1063/1.3248262]

Single-electron multiple-valued memory using ultra-small floating gate metal-oxide-semiconductor field effect transistor

This paper proposes a novel single-electron multiple-valued memory. It is a metal-oxide-semiconductor field effect transistor (MOS)-type memory with multiple separate control gates and floating gate layer, which consists of nano-crystal grains. The electron can tunnel among the grains (floating gates) and between the floating gate layer and the MOS channel. The memory can realize operations of 'write', 'store' and 'erase' of multiple-valued signals exceeding three values by controlling the single electron tunneling behavior. We use Monte Carlo method to simulate the operation of single-electron four-valued memory. The simulation results show that it can operate well at room temperature.

In situ doping control for growth of n-p-n Si/SiGe/Si heterojunction bipolar transistor by gas source molecular beam epitaxy

N-p-n Si/SiGe/Si heterostructures have been grown by a disilane (Si2H6) gas and Ge solid sources molecular beam epitaxy system using phosphine (PH3) and diborane (B2H6) as n- and p-type in situ doping sources, respectively. Adopting an in situ doping control technology, the influence of background B dopant on the growth of n-Si emitter layer was reduced, and an abrupt B dopant distribution from SiGe base to Si emitter layer was obtained. Besides, higher n-type doping in the surface region of emitter to reduce the emitter resist can be realized, and it did not result in the drop of growth rate of Si emitter layer in this technology. (C) 2004 Elsevier B.V. All rights reserved.

A novel hybrid phase-locked-loop frequency synthesizer using single-electron devices and CMOS transistors

This paper proposes a novel phase-locked loop (PLL) frequency synthesizer using single-electron devices (SEDs) and metal-oxide-semiconductor (MOS) field-effect transistors. The PLL frequency synthesizer mainly consists of a single-electron transistor (SET)/MOS hybrid voltage-controlled oscillator circuit, a single-electron (SE) turnstile/MOS hybrid phase-frequency detector (PFD) circuit and a SE turnstile/MOS hybrid frequency divider. The phase-frequency detection and frequency-division functions are realized by manipulating the single electrons. We propose a SPICE model to describe the behavior of the MOSFET-based SE turnstile. The authors simulate the performance of the PILL block circuits and the whole PLL synthesizer. Simulation results indicated that the circuit can well perform the operation of the PLL frequency synthesizer at room temperature. The PILL synthesizer is very compact. The total number of the transistors is less than 50. The power dissipation of the proposed PLL circuit is less than 3 uW. The authors discuss the effect of fabrication tolerance, the effect of background charge and the SE transfer accuracy on the performance of the PLL circuit. A technique to compensate parameter dispersions of SEDs is proposed.

A base-emitter self-aligned multi-finger Si1-xGex/Si power heterojunction bipolar transistor

With a crystal orientation dependent on the etch rate of Si in KOH-based solution, a base-emitter self-aligned large-area multi-linger configuration power SiGe heterojunction bipolar transistor (HBT) device (with an emitter area of about 880 mu m(2)) is fabricated with 2 mu m double-mesa technology. The maximum dc current gain is 226.1. The collector-emitter junction breakdown voltage BVCEO is 10 V and the collector-base junction breakdown voltage BVCBO is 16 V with collector doping concentration of 1 x 10(17) cm(-3) and thickness of 400 nm. The device exhibited a maximum oscillation frequency f(max) of 35.5 GHz and a cut-off frequency f(T) of 24.9 GHz at a dc bias point of I-C = 70 mA and the voltage between collector and emitter is V-CE = 3 V. Load pull measurements in class-A operation of the SiGe HBT are performed at 1.9 GHz with input power ranging from 0 dBm to 21 dBm. A maximum output power of 29.9 dBm (about 977 mW) is obtained at an input power of 18.5 dBm with a gain of 11.47 dB. Compared to a non-self-aligned SiGe HBT with the same heterostructure and process, f(max) and f(T) are improved by about 83.9% and 38.3%, respectively.

Quantum measurement characteristics of a double-dot single electron transistor

Owing to a few unique advantages, the double-dot single electron transistor has been proposed as an alternative detector for charge states. In this work, we present a further study for its signal-to-noise property, based on a full analysis of the setup configuration symmetry. It is found that the effectiveness of the double-dot detector can approach that of an ideal detector, if the symmetric capacitive coupling is taken into account. The quantum measurement efficiency is also analyzed by comparing the measurement time with the measurement-induced dephasing time.