人工神经网络在掩膜ROM测试方面的应用

Submitted by zhangdi (zhangdi@red.semi.ac.cn) on 2009-04-13T11:45:31Z

Novel approach to super-resolution pits readout

We proposed a novel method to realize the readout of super-resolution pits by using a super-resolution reflective film to replace the reflective layer of the conventional ROM. At the same time, by using Sb as the super-resolution reflective layer and SiN as a dielectric layer, the super-resolution pits with diameters of 380 nm were read out by a setup whose laser wavelength is 632.8 nm and numerical aperture is 0.40. In addition, the influence of the Sb thin film thickness on the readout signal was investigated, the results showed that the optimum Sb thin film thickness is 28 to 30 nm, and the maximum CNR is 38 to 40 dB. (C) 2002 Society of Photo-Optical Instrumentation Engineers.

Read-only memory disk with AgOx and AgInSbTe superresolution mask layer

Two novel read-only memory (ROM) disks, one with an AgOx mask layer and the other with an AgInSbTe mask layer, are proposed and studied. The AgOx and the AgInSbTe films sputtered on the premastered substrates with pit depths of 50 nm and pit lengths (space) of 380 nm are studied by atomic force microscopy. Disk readout measurement is carried out using a dynamic setup with a laser wavelength of 632.8 nm and an object lens numerical aperture (NA) of 0.40. Results show that the superresolution effect happens only at a suitable oxygen flow ratio for the AgOx ROM disk. The best superresolution readout effect is achieved at an oxygen flow ratio of 0.5 with the smoothest film surface. Compared with the AgOx ROM disk, the AgInSbTe ROM disk has a much smoother film surface and better superresolution effect. A carrier-to-noise ratio (CNR) of above 40 dB can be obtained at an appropriate readout power and readout velocity. The readout CNR of both the AgOx and AgInSbTe ROM disks have a nonlinear dependence on the readout power. The superresolution readout mechanisms for these ROM disks are analyzed and compared as well. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

Read-only memory disk with AgOx super-resolution mask layer

A novel read-only memory (ROM) disk with an AgOx mask layer was proposed and studied in this letter. The AgOx films sputtered on the premastered substrates, with pits depth of 50 nm and pits length of 380 nm, were studied by an atomic force microscopy. The transmittances of these AgOx films were also measured by a spectrophotometer. Disk measurement was carried out by a dynamic setup with a laser wavelength of 632.8 nm and a lens numerical aperture (NA) of 0.40. The readout resolution limit of this setup was λ/(4NA) (400 nm). Results showed that the super-resolution readout happened only when the oxygen flow ratios were at suitable values for these disks. The best super-resolution performance was achieved at the oxygen flow ratio of 0.5 with the smoothest film surface. The super-resolution readout mechanism of these ROM disks was analyzed as well.

Read-only memory disk with AgOx and AgInSbTe superresolution mask layer

Two novel read-only memory (ROM) disks, one with an AgOx mask layer and the other with an AgInSbTe mask layer, are proposed and studied. The AgOx and the AgInSbTe films sputtered on the premastered substrates with pit depths of 50 nm and pit lengths (space) of 380 nm are studied by atomic force microscopy. Disk readout measurement is carried out using a dynamic setup with a laser wavelength of 632.8 nm and an object lens numerical aperture (NA) of 0.40. Results show that the superresolution effect happens only at a suitable oxygen flow ratio for the AgOx ROM disk. The best superresolution readout effect is achieved at an oxygen flow ratio of 0.5 with the smoothest film surface. Compared with the AgOx ROM disk, the AgInSbTe ROM disk has a much smoother film surface and better superresolution effect. A carrier-to-noise ratio (CNR) of above 40 dB can be obtained at an appropriate readout power and readout velocity. The readout CNR of both the AgOx and AgInSbTe ROM disks have a nonlinear dependence on the readout power. The superresolution readout mechanisms for these ROM disks are analyzed and compared as well. (c) 2005 Society of Photo-Optical Instrumentation Engineers.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A high speed direct digital frequency synthesizer realized by a segmented nonlinear DAC

This paper presents a high speed ROM-less direct digital frequency synthesizer (DDFS) which has a phase resolution of 32 bits and a magnitude resolution of 10 bits. A 10-bit nonlinear segmented DAC is used in place of the ROM look-up table for phase-to-sine amplitude conversion and the linear DAC in a conventional DDFS.The design procedure for implementing the nonlinear DAC is presented. To ensure high speed, current mode logic (CML) is used. The chip is implemented in Chartered 0.35μm COMS technology with active area of 2.0 × 2.5 mm~2 and total power consumption of 400 mW at a single 3.3 V supply voltage. The maximum operating frequency is 850 MHz at room temperature and 1.0 GHz at 0 ℃.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

平台式FPGA中可重构存储器模块的设计

可重构静态存储器(SRAM)模块是场可编程门阵列(FPGA)的重要组成部分,它必须尽量满足用户不同的需要,所以要有良好的可重构性能.本文设计了一款深亚微米工艺下的16-kb的高速,低功耗双端口可重构SRAM.它可以重构成16Kx1,8Kx2,4Kx4,2Kx8,1Kx16和512x32六种不同的工作模式.基于不同的配置选择,此SRAM可以配置为双端口SRAM,单端口SRAM,ROM,FIFO,大的查找表或移位寄存器,本文完整介绍了该SRAM的设计方法,重点介绍了一种新颖的存储单元电路结构:三端口存储单元,以及用于实现可重构功能的电路的设计方法.

公平认证密钥交换协议的安全模型与模块化设计

传统的密钥交换协议通常假定合法通信双方都是可信的,然而很多现实应用都要求通信双方在互不信任的环境中执行认证密钥交换协议,为此本文提出了公平认证密钥交换(FAKE)的思想:除了具有一般认证密钥交换协议的基本特点外,通过客户在协议会话中预先植入"会话证据",使得在不揭示会话证据的前提下,合法通信双方均可以否认会话的发生;一旦客户方揭示会话证据,则协议会话记录就会与通信双方的身份绑定.该思想为解决网络服务中保护个人隐私与处理网络服务纠纷的矛盾提供了一种切实可行的技术解决思路.文中系统规划了公平认证密钥交换协议的形式化安全模型,纠正了Kudla关于并发签名公平性安全模型存在的错误之处,利用并发签名具体构造了一个公平认证密钥交换协议,并在随机预言模型(ROM)中证明了该协议满足mBJM-AK安全性、条件可否认性以及公平性.

基于TMS320VC5402控制系统并行引导方式设计

介绍了TMS320VC5402并行Bootloader的原理。为实现脱机运行,充分利用其片内掩膜ROM带有一个引导装载程序Bootloader,实现对用户程序的并行引导装载。同时采用CPLD编程技术提供了一种实用的扩展存储器设计方案。

高性能16位单片机80C196KC的应用

介绍了１６位８０Ｃ１９６ＫＣ单片机的独特性能．组成由８０Ｃ１９６ＫＣ单片机、存储器、光电编码器、模数转换器、键盘显示器、电机驱动电路等构成的测控系统．有针对性地提出了改进措施，并给出了ＨＳＯ的应用实例．