Flows with Inertia in a Three-Dimensional Random Fiber Network

A fiber web is modeled as a three-dimensional random cylindrical fiber network. Nonlinear behavior of fluid flowing through the fiber network is numerically simulated by using the lattice Boltzmann (LB) method. A nonlinear relationship between the friction factor and the modified Reynolds number is clearly observed and analyzed by using the Fochheimer equation, which includes the quadratic term of velocity. We obtain a transition from linear to nonlinear region when the Reynolds numbers are sufficiently high, reflecting the inertial effect of the flows. The simulated permeability of such fiber network has relatively good agreement with the experimental results and finite element simulations.

Adiabatic shear localization: occurrence, theories, and applications

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

A direct digital frequency synthesizer with single-stage delta-sigma interpolator and current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a 4th-order single-stage pipelined delta-sigma interpolator and a 300MS/s 12-bit current-steering DAC based on Q(2) Random Walk switching scheme. The delta-sigma interpolator is used to reduce the phase truncation error and the ROM size. The measured spurious-free dynamic range (SFDR) is greater than 80 dB for 8-bit phase value and 12-bit sine-amplitude output. The DDFS prototype is fabricated in a 0.35um CMOS technology with core area of 1.11mm(2).

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

多粒度多维度软件过程度量和改进方法研究

随着软件对社会各领域、各层次的渗透，软件逐渐转变为一种对社会团体、 甚至对社会公众的服务，软件的规模越来越大、用户需求越来越多、功能和性能 要求也越来越复杂。因此，对软件的可用性、可靠性、可信性等质量要求不断提 高。伴随着软件业的逐渐发展，软件过程技术逐渐被应用于软件产品的开发当中。 “质量形成于产品的生产过程”这一理念逐渐被软件组织所接受。其核心思想体 现在通过对软件过程的策划、控制和改进来保证软件产品的质量，进而提高软件 组织的经营业绩。软件过程度量作为软件过程管理和过程改进的关键活动，越来 越为软件组织所重视。 通过实施过程管理，能够刻画项目或过程目标的满足程度，找到造成过程 或产品重大偏差的根本原因，进而实施过程改进。然而，在软件过程度量实施期 间，软件组织面对不同的软件开发过程、众多的过程性能度量指标、复杂的统计 分析方法，既要考虑量化管理方法的合理性和复杂程度，又要权衡量化管理的实 施成本，这使得实施有效的过程度量充满挑战。本文基于经验软件工程方法，提 出一种多粒度多维度软件过程度量框架，以及实现该框架的关键技术：软件过程 性能基线的建立和维护方法；同时介绍了该框架下的软件项目进度量化控制模 型，支持软件组织实施有效的过程管理和改进。 本文的主要贡献包括： 提出了一种多粒度多维度软件过程度量框架(Multi-granularity Multi-dimensional software Process Measurement Framework，M2-PMF)，该框架通 过综合考虑软件过程管理和改进的必要信息所属的特征维度和软件组织的过程 管理粒度，自底向上的通过实体层、度量分析层和目标层指导软件组织建立一套 可以覆盖软件全生命周期的、开放的、支持过程改进的综合指标体系和模型。支 持软件组织裁减和定制确定环境下的度量体系，清晰了解其软件过程能力和性 能，提高软件组织对软件过程的控制能力，保障软件开发过程和软件产品的质量。 提出了基于统计分析的过程性能基线的建立和改进方法（Baseline – Statistic - Refinement， BSR），该方法可以有效地建立和维护过程性能基线，支持软件 组织从定性管理提升到定量管理。该方法应用波动图，在过程尚不稳定、数据样 本不足的情况下尽可能多的获得过程改进信息，识别过程改进机会，确定过程改 进途径，帮助软件组织高效地改进其过程中明显的弱项。在过程逐步稳定之后， 利用控制图、排列图、因果图、散点图等统计工具，分析过程性能，建立过程性 多粒度多维度软件过程度量和改进方法研究 ii 能基线，并不断精化。 在M2-PMF 框架下，提出了基于统计过程控制（Statitical Process Control， SPC）和挣值管理（Earned Value Management，EVM）的项目进度量化控制模型 SEVM，该方法通过对项目进度指数的统计控制，分析其稳定性，并通过估算模 型，根据项目当前挣值数据推算项目总进度偏差，并加以控制。支持软件组织对 项目进度进行量化控制，提高了项目按期交付的可能性。 最后，介绍了本文提出的过程度量框架和量化管理方法在国内多家软件组 织中的实际应用。应用案例表明，本文的方法和模型具有广泛的适应性和高度的 可操作性。应用本文方法能够对项目进行有效的估算、度量和控制，进而提高产 品质量并改善客户满意度。

面向高速应用的10位2GHz数模转换器

提出了一个刷新率达2GHz的10位电流驱动型数模转换器.在综合了精度与芯片面积等因素之后,该数模转换器使用6+4结构.采用电流型逻辑以提高转换器的速度,并采用Q~2 random walk方法设计了一个双中心对称的电流矩阵,确保数模转换器的线性度.该数模转换器核心版图面积为2.2mm×2.2mm,在3.3V单电压供电的情况下,该芯片功耗为790mW.

A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

Web-based spatiotemporal visualization of marine environment data

With long-term marine surveys and research, and especially with the development of new marine environment monitoring technologies, prodigious amounts of complex marine environmental data are generated, and continuously increase rapidly. Features of these data include massive volume, widespread distribution, multiple-sources, heterogeneous, multi-dimensional and dynamic in structure and time. The present study recommends an integrative visualization solution for these data, to enhance the visual display of data and data archives, and to develop a joint use of these data distributed among different organizations or communities. This study also analyses the web services technologies and defines the concept of the marine information gird, then focuses on the spatiotemporal visualization method and proposes a process-oriented spatiotemporal visualization method. We discuss how marine environmental data can be organized based on the spatiotemporal visualization method, and how organized data are represented for use with web services and stored in a reusable fashion. In addition, we provide an original visualization architecture that is integrative and based on the explored technologies. In the end, we propose a prototype system of marine environmental data of the South China Sea for visualizations of Argo floats, sea surface temperature fields, sea current fields, salinity, in-situ investigation data, and ocean stations. An integration visualization architecture is illustrated on the prototype system, which highlights the process-oriented temporal visualization method and demonstrates the benefit of the architecture and the methods described in this study.

The electrochemical behavior of a system with a limited number of molecules

In this paper, based on Einstein relationship between diffusion and random walk, the electrochemical behavior of a system with a limited number of molecules was simulated and explored theoretically. The transition of the current vs time responses from discrete to continuous was clearly obtained as the number of redox molecules increased from 10 to 10(6).

The time delay in electrochemical measurements of a finite-volume system

For a sphere electrode enclosed in finite-volume electrolyte, the measured current will deviate from the result predicted by the semi-infinite diffusion theory after some time. By random-walk simulation, we compared this time to the one needed for diffusion layer to reach electrolyte boundary, and revealed a clear signal delay of electrochemical current. Further we presented a quantitative description of this delay time. The simulation results suggested that the semi-infinite diffusion theory can even be applied when the theoretical diffusion layer grows to 1.28 electrolyte thicknesses, with an accuracy better than 0.5%. We attributed this time delay to the molecules' finite propagation velocity. Finally, we discussed how this delay can influence and facilitate the following electrochemical detection towards the nanometer and single-cell scale.