A 12bit 300MHz Current-Steering CMOS D/A Converter

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

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国家高技术研究发展计划资助项目

Institute of Semiconductors, Chinese Academy of Sciences

国家高技术研究发展计划资助项目