Performance analysis of bit error rate for free space optical communication with tip-tilt compensation based on gamma-gamma distribution

In this paper, the gamma-gamma probability distribution is used to model turbulent channels. The bit error rate (BER) performance of free space optical (FSO) communication systems employing on-off keying (OOK) or subcarrier binary phase-shift keying (BPSK) modulation format is derived. A tip-tilt adaptive optics system is also incorporated with a FSO system using the above modulation formats. The tip-tilt compensation can alleviate effects of atmospheric turbulence and thereby improve the BER performance. The improvement is different for different turbulence strengths and modulation formats. In addition, the BER performance of communication systems employing subcarrier BPSK modulation is much better than that of compatible systems employing OOK modulation with or without tip-tilt compensation.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

Highly coherent solid-state quantum bit from a pair of quantum dots

In this letter, we propose a scheme to buildup a highly coherent solid-state quantum bit (qubit) from two coupled quantum dots. Quantum information is stored in the state of the electron-hole pair with the electron and hole located in different dots, and universal quantum gates involving any pair of qubits are realized by effective coupling interaction via virtually exchanging cavity photons. (C) 2002 American Institute of Physics.

A 10-bit 2GHz current-steering CMOS D/A converter

This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

A 12-bit 300 MHz CMOS DAC for high-speed system applications

This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

A direct digital frequency synthesizer with fourth-order phase domain Delta Sigma noise shaper and 12-bit current-steering DAC

This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold (S/H) circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter (ADC) was designed and fabricated using a 0.35-μm CMOS process. Capacitor fliparound architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier (OTA) was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range (SFDR) of 67 dB and a signal-to-noise ratio (SNR) of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12 mm~2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

Simple lattice Boltzmann model for traffic flows

A lattice Boltzmann model with 5-bit lattice for traffic flows is proposed. Using the Chapman-Enskog expansion and multi-scale technique, we obtain the higher-order moments of equilibrium distribution function. A simple traffic light problem is simulated by using the present lattice Boltzmann model, and the result agrees well with analytical solution.

A lattice Boltzmann method for KDV equation

We prepose a 5-bit lattice Boltzmann model for KdV equation. Using Chapman-Enskog expansion and multiscale technique, we obtained high order moments of equilibrium distribution function, and the 3rd dispersion coefficient and 4th order viscosity. The parameters of this scheme can be determined by analysing the energy dissipation.

利用原子芯片上Z形磁阱囚禁中性^87Rb原子

利用解析和数值方法计算了Z形磁阱的囚禁势,发现当囚禁中心和芯片表面距离较远时（该距离和Z形线中部导线的一半长度相差不超过一个量级）,势阱的深度不能近似表示成偏置磁场By对应的能量,而要减去囚禁中心的势能高度;而增加By进行磁阱压缩到一定值时,势阱深度反而会下降.此外介绍了原子芯片的制作方法,以及利用原子芯片上Z形磁阱囚禁中性87Rb原子的实验装置和实验过程.最终有2×10^6个^87Rb原子被转移到Z形磁阱中.