The fabrication of GaN-based nanopillar light-emitting diodes

InGaN/GaN multiple quantum well-based light-emitting diode (LED) nanopillar arrays were fabricated using Ni self-assembled nanodots as etching mask. The Ni nanodots were fabricated with a density of 6 x 10(8)-1.5 x 10(9) cm(-2) and a dimension of 100-250 nm with varying Ni thickness and annealing duration time. Then LED nanopillar arrays with diameter of approximately 250 nm and height of 700 nm were fabricated by inductively coupled plasma etching. In comparison to the as-grown LED sample an enhancement by a factor of four of photoluminescence (PL) intensity is achieved for the nanopillars and a blueshift as well as a decrease in full width at half maximum of the PL peak are also observed. The method of additional chemical etching was used to remove the etching-induced damage. Then nano-LED devices were further completed using a planarization approach to deposit p-type electrode on the tips of nanopillars. The current-voltage curves of both nanopillars and planar LED devices are measured for comparison.

Fabrication of Silicon-Based Template-Assisted Nanoelectrode Arrays and Ohmic Contact Properties Investigation

A convenient fabrication technology for large-area, highly-ordered nanoelectrode arrays on silicon substrate has been described here, using porous anodic alumina (PAA) as a template. The ultrathin PAA membranes were anodic oxidized utilizing a two-step anodization method, from Al film evaporated on substrate. The purposes for the use of two-step anodization were, first, improving the regularity of the porous structures, and second reducing the thickness of the membranes to 100 similar to 200 nm we desired. Then the nanoelectrode arrays were obtained by electroless depositing Ni-W alloy into the through pores of PAA membranes, making the alloy isolated by the insulating pore walls and contacting with the silicon substrates at the bottoms of pores. The Ni-W alloy was also electroless deposited at the back surface of silicon to form back electrode. Then ohmic contact properties between silicon and Ni-W alloy were investigated after rapid thermal annealing. Scanning electron microscopy (SEM) observations showed the structure characteristics, and the influence factors of fabrication effect were discussed. The current voltage (I-V) curves revealed the contact properties. After annealing in N-2 at 700 degrees C, good linear property was shown with contact resistance of 33 Omega, which confirmed ohmic contacts between silicon and electrodes. These results presented significant application potential of this technology in nanosize current-injection devices in optoelectronics, microelectronics and bio-medical fields.

A COMPARATIVELY LOW-QUALITY SILICON MATERIAL IMPROVED FOR SOLAR-CELL FABRICATION

A comparatively low-quality silicon wafer (with a purity of almost-equal-to 99.9%) was adopted to form a silicon-on-defect-layer (SODL) structure featuring improved crystalline silicon near the defect layer (DL) by means of proton implantation and subsequent annealing. Thus, the SODL technique provides an opportunity to enable low-quality silicon wafers to be used for fabrication of low-cost solar cells.

High efficiency AlxGa1-xAs/GaAs solar cells: Fabrication, irradiation and annealing effect

High efficiency AlxGa1-xAs/GaAs heteroface solar cells have been fabricated by an improved multi-wafer squeezing graphite boat liquid phase epitaxy (LPE) technique, which enables simultaneous growth of twenty 2.3 X 2.3cm(2) epilayers in one run. A total area conversion efficiency of 17.33% is exhibited (1sun, AM0, 2.0 x 2.0cm(2)). The shallow junction cell shows more resistance to 1 MeV electron radiation than the deep one. After isochronal or isothermal annealing the density and the number of deep level traps induced by irradiation are reduced effectively for the solar cells with deep junction and bombardment under high electron fluences.

Lithography-independent and large scale fabrication of a metal electrode nanogap

A lithography-independent and wafer scale method to fabricate a metal nanogap structure is demon-strated. Polysilicon was first dry etched using photoresist (PR) as the etch mask patterned by photolithography.Then, by depositing conformal SiO_2 on the polysilicon pattern, etching back SiO_2 anisotropically in the perpendic-ular direction and removing the polysilicon with KOH, a sacrificial SiO_2 spacer was obtained. Finally, after metal evaporation and lifting-off of the SiO_2 spacer, an 82 nm metal-gap structure was achieved. The size of the nanogap is not determined by the photolithography, but by the thickness of the SiO_2. The method reported in this paper is compatible with modern semiconductor technology and can be used in mass production.

Fabrication of Silicon Crystal-Facet-Dependent Nanostructures by Electron-Beam Lithography

Silicon crystal-facet-dependent nanostructures have been successfully fabricated on a (100)-oriented silicon-on-insulator wafer using electron-beam lithography and the silicon anisotropic wet etching technique. This technique takes ad-vantage of the large difference in etching properties for different crystallographic planes in alkaline solution. The mini-mum size of the trapezoidal top for those Si nanostructures can be reduced to less than 10nm. Scanning electron microscopy(SEM) and atomic force microscopy (AFM) observations indicate that the etched nanostructures have controllable shapes and smooth surfaces.

Fabrication of an AlAs/In0.53Ga0.47As/InAs Resonant Tunneling Diode on InP Substrate for High-Speed Circuit Applications

A high performance AlAs/In0.53 Ga0.47 As/InAs resonant tunneling diode （RTD） on InP substrate is fabricated by inductively coupled plasma etching. This RTD has a peak-to-valley current ratio （PVCR） of 7. 57 and a peak current density Jp = 39.08kA/cm^2 under forward bias at room temperature. Under reverse bias, the corresponding values are 7.93 and 34.56kA/cm^2 . A resistive cutoff frequency of 18.75GHz is obtained with the effect of a parasitic probe pad and wire. The slightly asymmetrical current-voltage characteristics with a nominally symmetrical structure are also discussed.

Fabrication of a Silicon-Based Microprobe for Neural Interface Applications

A two-dimensional (2D) multi-channel silicon-based microelectrode array is developed for recording neural signals. Three photolithographic masks are utilized in the fabrication process. SEM images show that the microprobe is 1. 2mm long,100μm wide,and 30μm thick, with recording sites spaced 200μm apart for good signal isolation. For the individual recording sites, the characteristics of impedance versus frequency are shown by in vitro testing. The impedance declines from 14MΩ to 1.9kv as the frequency changes from 0 to 10MHz. A compatible PCB (print circuit board) aids in the less troublesome implantation and stabilization of the microprobe.

Design and Fabrication of Power Si1-xGex/Si Heterojunction Bipolar Transistor for Wireless Power Amplifier Applications

A multi-finger structure power SiGe HBT device （with an emitter area of about 166μm^2） is fabricated with very simple 2μm double-mesa technology. The DC current gain β is 144.25. The B-C junction breakdown voltage reaches 9V with a collector doping concentration of 1 × 10^17cm^-3 and a collector thickness of 400nm. Though our data are influenced by large additional RF probe pads, the device exhibits a maximum oscillation frequency fmax of 10.1GHz and a cut-off frequency fτ of 1.8GHz at a DC bias point of IC=10mA and VCE = 2.5V.