The design algorithm of an associative memory neural network

A design algorithm of an associative memory neural network is proposed. The benefit of this design algorithm is to make the designed associative memory model can implement the hoped situation. On the one hand, the designed model has realized the nonlinear association of infinite value pattern from n dimension space to m dimension space. The result has improved the ones of some old associative memory neural network. On the other hand, the memory samples are in the centers of the fault-tolerant. In average significance the radius of the memory sample fault-tolerant field is maximum.

Study on Mg memory effect in npn type AlGaN/GaN HBT structures grown by MOCVD

AlGaN/GaN npn heterojunction bipolar transistor structures were grown by low-pressure MOCVD. Secondary ion mass spectroscopy (SIMS) measurements were carried out to study the Mg memory effect and redistribution in the emitter-base junction. The results indicated that there is a Mg-rich film formed in the ongrowing layer after the Cp2Mg source is switched off. The Mg-rich film can be confined in the base section by switching off the Cp2Mg source for appropriate time before the end of base growth. Low temperature growth of the undoped GaN spacer suppresses the Mg redistribution from Mg rich film. The delay rate of the Mg profile in sample C with spacer growing in low temperature is about 56 nm/decade, which becomes sharper than 80 nm/decade of the samples A and B without low temperature spacer. (C) 2005 Elsevier Ltd. All rights reserved.

Shape and spatial correlation control of InAs-InAlAs-InP(001) nanostructure superlattices

The control of shape and spatial correlation of InAs-InAlAs-InP(001) nanostructure superlattices has been realized by changing the As overpressure during the molecular-beam epitaxy (MBE) growth of InAs layers. InAs quantum wires (QWRs) are obtained under higher As overpressure (1x10(-5) Torr), while elongated InAs quantum dots (QDs) are formed under lower As overpressure (5x10(-6) or 2.5x10(-6) Torr). Correspondingly, spatial correlation changes from vertical anti-correlation in QWR superlattices to vertical correlation in QD superlattices, which is well explained by the different alloy phase separation in InAlAs spacer layers triggered by the InAs nanostrcutures. It was observed that the alloy phase separation in QD superlattices could extend a long distance along the growth direction, indicating the vertical correlation of QD superlattices can be kept in a wide range of spacer layer thickness.

Photon-storage in optical memory cells based on a semiconductor quantum dot-quantum well hybrid structure

We report a new type of photonic memory cell based on a semiconductor quantum dot (QD)-quantum well (QW) hybrid structure, in which photo-generated excitons can be decomposed into separated electrons and holes, and stored in QW and QDs respectively. Storage and retrieval of photonic signals are verified by time-resolved photoluminescence experiments. A storage time in excess of 100ms has been obtained at a temperature of 10 K while the switching speed reaches the order of ten megahertz.

Changing the size and shape of Ge island by chemical etching

Self-assembled Ge islands were grown on Si (1 0 0) substrate by Si2H6-Ge molecular beam epitaxy. Subjected to a chemical etching, it is found that the size and shape (i.e. ratio of height to base width) of Ge islands change with etching time. In addition, the photoluminescence from the etched Ge islands shifted to the higher energy side compared to that of the as-deposited Ge islands. Our results demonstrated that chemical etching can be a way to change the size and shape of the as-deposited islands as well as their luminescence property. (C) 2001 Elsevier Science B.V. All rights reserved.

Size and shape evolution of self-assembled coherent InAs/GaAs quantum dots influenced by seed layer

The size and shape Evolution of self-assembled InAs quantum dots (QDs) influenced by 2.0-ML InAs seed layer has been systematically investigated for 2.0, 2.5, and 2.9-ML deposition on GaAs(1 0 0) substrate. Based on comparisons with the evolution of InAs islands on single layer samples at late growth stage, the bimodal size distribution of InAs islands at 2.5-ML InAs coverage and the formation of larger InAs quantum dots at 2.9-ML deposition have been observed on the second InAs layer. The further cross-sectional transmission electron microscopy measurement indicates the larger InAs QDs: at 2.9-ML deposition on the second layer are free of dislocation. In addition, the interpretations for the size and shape evolution of InAs/GaAs QDs on the second layer will be presented. (C) 2001 Elsevier Science B.V. All lights reserved.

Shape evolution of Ge/Si(001) islands induced by strain-driven alloying

The shape evolution of Ge/Si(001) islands grown by ultrahigh vacuum chemical vapor deposition were investigated by atomic force microscopy at different deposition rates. We find that, at low deposition rates, the evolution of islands follows the conventional pathway by which the islands form the pyramid islands, evolve into dome islands, and dislocate at a superdome shape with increasing coverage. While at a high deposition rate of 3 monolayers per minute, the dome islands evolve towards the pyramids by a reduction of the contact angle. The presence of the atomic intermixing between the Ge islands and Si substrate at high deposition rate is responsible for the reverse evolution. (C) 2001 American Institute of Physics.

In-Situ Boron and Aluminum Doping and Their Memory Effects in 4H-SiC Homoepitaxial Layers Grown by Hot-Wall LPCVD

The in-situ p-type doping of 4H-SiC grown on off-oriented (0001) 4H-SiC substrates was performed with trimethylaluminum (TMA) and/or diborane (B2H6) as the dopants. The incorporations of Al and B atoms and their memory effects and the electrical properties of p-type 4H-SiC epilayers were characterized by secondary ion mass spectroscopy (SIMS) and Hall effect measurements, respectively. Both Al- and B-doped 4H-SiC epilayers were p-type conduction. It was shown that the profiles of the incorporated boron and aluminum concentration were in agreement with the designed TMA and B2H6 flow rate diagrams. The maximum hole concentration for the Al doped 4H-SiC was 3.52x10(20) cm(-3) with Hall mobility of about 1 cm(2)/Vs and resistivity of 1.6 similar to 2.2x10(-2) Omega cm. The heavily boron-doped 4H-SiC samples were also obtained with B2H6 gas flow rate of 5 sccm, yielding values of 0.328 Omega cm for resistivity, 5.3x10(18) cm(-3) for hole carrier concentration, and 7 cm(2)/VS for hole mobility. The doping efficiency of Al in SiC is larger than that of B. The memory effects of Al and B were investigated in undoped 4H-SiC by using SIMS measurement after a few run of doped 4H-SiC growth. It was clearly shown that the memory effect of Al is stronger than that of B. It is suggested that p-type 4H-SiC growth should be carried out in a separate reactor, especially for Al doping, in order to avoid the join contamination on the subsequent n-type growth. 4H-SiC PiN diodes were fabricated by using heavily B doped epilayers. Preliminary results of PiN diodes with blocking voltage of 300 V and forward voltage drop of 3.0 V were obtained.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Self-assembled GaAs quantum rings by MBE droplet epitaxy

Fabrication of semiconductor nanostructures such as quantum dots (QDs), quantum rings (QRs) has been considered as the important step for realization of solid state quantum information devices, including QDs single photon emission source, QRs single electron memory unit, etc. To fabricate GaAs quantum rings, we use Molecular Beam Epitaxy (MBE) droplet technique in this report. In this droplet technique, Gallium (Ga) molecular beams are supplied initially without Arsenic (As) ambience, forming droplet-like nano-clusters of Ga atoms on the substrate, then the Arsenic beams are supplied to crystallize the Ga droplets into GaAs crystals. Because the morphologies and dimensions of the GaAs crystal are governed by the interplay between the surface migration of Ga and As adatoms and their crystallization, the shape of the GaAs crystals can be modified into rings, and the size and density can be controlled by varying the growth temperatures and As/Ga flux beam equivalent pressures(BEPs). It has been shown by Atomic force microscope (AFM) measurements that GaAs single rings, concentric double rings and coupled double rings are grown successfully at typical growth temperatures of 200 C to 300 C under As flux (BEP) of about 1.0 x 10(-6) Torr. The diameter of GaAs rings is about 30-50 nm and thickness several nm.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Fully lithography independent fabrication of nanogap electrodes for lateral phase-change random access memory application

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