A new interface anisotropic potential of zinc-blende semiconductor interface induced by lattice mismatch

A new interface anisotropic potential, which is proportional to the lattice mismatch of interfaces and has no fitting parameter, has been deduced for (001) zinc-blende semiconductor interfaces. The comparison with other interface models is given for GaAs/AlAs and GaAs/InAs interfaces. The strong influence of the interface anisotropic potential on the inplane optical anisotropy of GaAs/AlGaAs low dimensional structures is demonstrated theoretically within the envelope function approximation.

A study of the interface of CeO2/Si heterostructure grown by ion beam deposition

Epitaxial cerium dioxide films on single-crystal silicon substrates (CeO2/Si) have been grown by a dual mass-analyzed low-energy ion beam deposition (IBD) system. By double-crystal X-ray diffraction (XRD), Full Width at Half Maximum (FWHM) are 23' and 33' in the rocking curves for (222) and (111) faces of the CeO2 film, respectively, and the lattice-mismatch Delta a/a with the substrate is about - 0.123%. The results show that the CeO2/Si grown by IBD is of high crystalline quality. In this work, the CeO2/Si heterostructure were investigated by X-ray Photoelectron Spectroscopy (XPS) and Auger Electron Spectroscopy (AES) measurements. Especially, XPS and AES depth profiling was used to analyze the compositions and structures in the interface regions of the as-grown and post-annealed CeO2/Si. It was found that there was no silicon oxide in the interface region of the as-grown sample but silicon oxide in the post-annealed sample. The reason for obtaining such high quality heterostructure mainly depends on the absence of silicon oxide in the surface at the beginning of the deposition. (C) 1998 Elsevier Science Ltd. All rights reserved.

Effect of reflectivity at the interface of oxide layer on transverse mode control in oxide confined vertical-cavity surface-emitting lasers

The transverse mode control in oxide confined vertical-cavity surface-emitting lasers is discussed by modeling the dielectric aperture as a uniform waveguide and an extra reflectivity at the oxide layer. The phase of the extra reflectivity and the refractive index step can be adjusted to change the mode threshold gain. We calculate the lateral refractive index step from the mode wavelength difference between aperture and perimeter modes, and compare it with that obtained from the weighted average index. The mode reflectivity in terms of the lateral optical confinement factor at the oxide layer is considered in calculating the threshold gain for transverse modes. The numerical results show that higher transverse modes can be suppressed by adjusting the position of a thin AlAs-oxide layer inside a three-quarter-wave layer in the distributed Bragg reflector. (C) 1998 American Institute of Physics. [S0021-8979(98)04007-9].

Heteroepitaxy of cubic GaN: influence of interface structure

We report on the epitaxial growth and the microstructure of cubic GaN. The layers are deposited by plasma-assisted molecular beam epitaxy on GaAs and Si substrates. Despite the extreme lattice mismatch between these materials, GaN grows in the metastable cubic phase with a well-defined orientation-relationship to the GaAs substrate including a sharp heteroboundary. The preference of the metastable phase and its epitaxial orientation originates in the interface structure which is found to be governed by a coincidence site lattice.

A novel ultra low power temperature sensor for UHF RFID tag chip

A novel ultra low power temperature sensor for UHF RFID tag chip is presented. The sensor consists of a constant pulse generator, a temperature related oscillator, a counter and a bias. Conversion of temperature to digital output is fulfilled by counting the number of the clocks of the temperature related oscillator in a constant pulse period. The sensor uses time domain comparing, where high power consumption bandgap voltage references and traditional ADCs are not needed. The sensor is realized in a standard 0.18 mu m CMOS process, and the area is only 0.2mm(2). The accuracy of the temperature sensor is +/- 1 degrees C after calibration. The power consumption of the sensor is only 0.9 mu W.

A Novel Low-Power Digital Baseband Circuit for UHF RFID Tag with Sensors

A novel low-power digital baseband circuit for UHF RFID tag with sensors is presented in this paper. It proposes a novel baseband architecture and a new operating scheme to fulfill the sensor functions and to reduce power consumption. It is also compatible with the EPC C1G2 UHF RFID protocol. It adopts some advanced low power techniques for system design and circuit design: adaptive clock-gating, multi-clock domain and asynchronous circuit. The baseband circuit is implemented in 0.18um 1P3M standard CMOS process. ne chip area is 0.28 mm(2) excluding test pads. Its power consumption is 25uW under 1.1V power supply.

High efficiency RFID UHF power converter

The paper proposes a high efficiency RFID UHF power converter unit to overcome the low efficiency problem. This power converter is mainly composed of an RF-DC converter and a DC-DC converter. In order to overcome the low efficiency problem in low current consuming condition, a DC-DC converter is added to conventional single RF-DC converter rectifier to increase the rectifying efficiency of the RFDC rectifier. The power converter is implemented in a 0.18 um mixed signal, 1p6m CMOS technology. Simulation shows the power converter has an average improvement of 5% and can achieve efficiency as high as 30% with 900MHz, 16uW RF input power and 1.3 V 3.6uA DC output.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

Influence of interface modification on the performance of polymer/Bi2S3 nanorods bulk heterojunction solar cells

In this paper, bulk heterojunction photovoltaic devices based on the poly[2-methoxy-5-(3',7'-dimethyloctyloxy)- 1,4-phenylenevinylene] (MDMO-PPV):Bi2S3 nanorods hybrid material were present. To optimize the performance of the devices, the interface modification of the hybrid material that has a significant impact on the exciton dissociation efficiency was studied. An improvement in the device performance was achieved by modifying the Bi2S3 surface with a thin dye layer. Moreover, modifying the Bi2S3 surface with anthracene-9-carboxylic acid can enhance the performance further. Compared with the solar cells with Bi2S3 nanorods hybrid with the MDMO-PPV as the active layer, the anthracene-9carboxylic acid modified devices are better in performance, with the power conversion efficiency higher by about one order in magnitude.

RFID安全协议的设计与分析

回顾了已有的各种RFID安全机制,重点介绍基于密码技术的RFID安全协议;分析了这些协议的缺陷;讨论了基于可证明安全性理论来设计和分析RFID安全协议的模型和方法.

scenario-focused development method for a pen-based user interface: model and applications

Pen-based user interface (PUI) has drawn significant interest, owing to its intuitiveness and convenience. While much of the research focuses on the technology, the usability of a PUI has been relatively low since human factors have not been considered sufficiently. Scenario-centric designs are ideal ways to improve usability. However, such designs possess some problems in practical use. To cope with these design issues, the concept of “interface scenarios” is proposed in to facilitate the interface design, and to help users understand the interaction process in such designs. The proposed scenario-focused development method for PUI is coupled with a practical application to show its effectiveness and usability.

A New Criterion Number for the Boundary Conditions at the Solid/Liquid Interface in Nanoscale

A simple, but important three-atom model was proposed at the solid/liquid interface, leading to a new criterion number, lambda, governing the boundary conditions (BCs) in nanoscale. The solid wall is considered as the face-centered-cubic (fcc) structure. The fluid is the liquid argon with the well-known LJ potential. Based on the concept, the two micro-systems have the same BCs if they have The same criterion number. The degree of the locking BCs is enhanced when lambda equals to 0.757. Such critical criterion number results in the substantial epitaxial ordering and one, two, or even three liquid layers are locked by the solid wall, depending on the coupling energy scale ratio of the solid and liquid atoms. With deviation from the critical criterion number, the flow approaches the slip BCs and there are little ordering structures within the liquid. Always at the same criterion number, the degree of the slip is decreased or the locking is enhanced with increasing the coupling energy scale ratio of the solid and liquid atoms. The above analysis is well confirmed by the molecular dynamics (MD) simulation. The slip length is well correlated in terms of the new criterion number. The future work is suggested to extend the present theory for other microstructures of the solid wall atoms and quasi-LJ potentials.

PHOTOELECTROCHEMICAL BEHAVIOR OF THE GAAS/ALXGA1-XAS SUPERLATTICE ELECTRODE/ELECTROLYTE INTERFACE

Single and multiple quantum wells of lattice-matched superlattices material GaAs/AlxGa1-xAs have been studied as photoelectrodes in photoelectrochemical cells containing nonaqueous electrolyte. Structural photocurrent spectra in the potential range of -1.8 to 1.0 V (vs standard calomel electrode) were obtained. The quantum yields for both superlattice electrodes were estimated and compared.