Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

The design and verification of FPGA CAD toolset

This paper introduces a complete CAD toolset for the implementation of digital logic in a Field-Programmable Gate Array (FPGA) platform. Compared with existing academic toolsets, this toolset introduces formal verification in each step of the tool flow, especially the formal verification of the configuration bitstream. The FPGA CAD tool verification flow using Formality is presented in detail. Using plug-in technology, we have developed an integrated FPGA design kit to incorporate all tools together.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Pipeline Architecture and Parallel Computation-Based Real-Time Stereovision Tracking System for Surgical Navigation

This paper studies the development of a real-time stereovision system to track multiple infrared markers attached to a surgical instrument. Multiple stages of pipeline in field-programmable gate array (FPGA) are developed to recognize the targets in both left and right image planes and to give each target a unique label. The pipeline architecture includes a smoothing filter, an adaptive threshold module, a connected component labeling operation, and a centroid extraction process. A parallel distortion correction method is proposed and implemented in a dual-core DSP. A suitable kinematic model is established for the moving targets, and a novel set of parallel and interactive computation mechanisms is proposed to position and track the targets, which are carried out by a cross-computation method in a dual-core DSP. The proposed tracking system can track the 3-D coordinate, velocity, and acceleration of four infrared markers with a delay of 9.18 ms. Furthermore, it is capable of tracking a maximum of 110 infrared markers without frame dropping at a frame rate of 60 f/s. The accuracy of the proposed system can reach the scale of 0.37 mm RMS along the x- and y-directions and 0.45 mm RMS along the depth direction (the depth is from 0.8 to 0.45 m). The performance of the proposed system can meet the requirements of applications such as surgical navigation, which needs high real time and accuracy capability.

Valence band offset of MgO/TiO2 (rutile) heterojunction measured by X-ray photoelectron spectroscopy

The valence band offset (VBO) of MgO/TiO2 (rutile) heterojunction has been directly measured by Xray photoelectron spectroscopy. The VBO of the heterojunction is determined to be 1.6 +/- 0.3 eV and the conduction band offset (CBO) is deduced to be 3.2 +/- 0.3 eV, indicating that the heterojunction exhibits a type-I band alignment. These large values are sufficient for MgO to act as tunneling barriers in TiO2 based devices. The accurate determination of the valence and conduction band offsets is important for use of MgO as a buffer layer in TiO2 based field-effect transistors and dye-sensitized solar cells.

Short range scattering mechanism of type-II GaSb/GaAs quantum dots on the transport properties of two-dimensional electron gas

We have studied the scattering process of AlGaAs/GaAs two-dimensional electron gas with the nearby embedded GaSb/GaAs type-II quantum dots (QDs) at low temperature. Quantum Hall effect and Shubnikov-de Haas oscillation were performed to measure the electron density n(2D), the transport lifetime tau(t) and the quantum lifetime tau(q) under various biased gate voltage. By comparing measured results of QDs sample with that of reference sample without embedded QDs, mobilities (transport mobility mu(t) and quantum mobility mu(q)) dominated by GaSb QDs scattering were extracted as functions of n(2D). It was found that the ratios of tau(t) to tau(q) were varying within the range of 1-4, implying the scattering mechanism belonging to the sort of short-range interaction. In the framework of Born approximation, a scattering model considering rectangular-shaped potential with constant barrier height was successfully applied to explain the transport experimental data. In addition, an oscillating ratio of tau(t)/tau(q) with the increasing n(2D) was predicted in the model.

Real-time data processing of interferential imaging spectrometer based on FPGA

Based on the data processing technologies of interferential spectrometer, a sort of real-time data processing system on chip of interferential imaging spectrometer was studied based on large capacitance and high speed field programmable gate array( FPGA) device. The system integrates both interferograrn sampling and spectrum rebuilding on a single chip of FPGA and makes them being accomplished in real-time with advantages such as small cubage, fast speed and high reliability. It establishes a good technical foundation in the applications of imaging spectrometer on target detection and recognition in real-time.

长期水分胁迫下氮、钾对夏玉米叶片光合特性的影响

采用2种不同夏玉米基因型(陕单9号,抗旱品种;陕单911,不抗旱品种)的盆栽试验,研究了长期水分胁迫下氮、钾对各生育期叶片净光合速率、蒸腾速率、胞间二氧化碳浓度和叶绿素含量的影响,旨在从光合生理特性揭示这些因子的抗旱机理。结果表明,长期水分胁迫下叶片净光合速率,蒸腾速率、胞间二氧化碳浓度(除成熟期)和叶绿素含量显著降低,不抗旱品种降幅更甚。抗旱品种的净光合速率和叶绿素含量大于不抗旱品种,而蒸腾速率和胞间二氧化碳浓度则相反。两品种苗期光合作用较弱,净光合速率和叶绿素含量均较低,抽雄期达到高峰。施氮能不同程度降低水分胁迫下玉米叶片的蒸腾速率,增加叶绿素含量.提高净光合速率,从而减缓水分胁迫对光合作用的伤害。随氮肥用量增加,不抗旱品种净光合速率和叶绿素含量显著升高,蒸腾速率和胞间二氧化碳浓度明显降低,两种氮肥用量间有显著差异;抗旱品种在低氮用量时效果显著,但高低氮用量间无显著区别。钾对受水分胁迫的玉米表现出比氮肥更突出的效果。相反,在适量供水条件下,氮、钾肥的作用明显下降。以上结果表明,适当用量的氮、钾肥可以有效地改善水分胁迫下作物叶片的光合特性,从而增强作物的抗旱性。

Electron tunneling through double magnetic barriers on the surface of a topological insulator

We study electron tunneling through a planar magnetic and electric barrier on the surface of a three-dimensional topological insulator. For the double barrier structures, we find (i) a directional-dependent tunneling which is sensitive to the magnetic field configuration and the electric gate voltage, (ii) a spin rotation controlled by the magnetic field and the gate voltage, (iii) many Fabry-Perot resonances in the transmission determined by the distance between the two barriers, and (iv) the electrostatic potential can enhance the difference in the transmission between the two magnetization configurations, and consequently lead to a giant magnetoresistance. Points (i), (iii), and (iv) are alike with that in graphene stemming from the same linear-dispersion relations.

STUDIES OF THE PROMISING MATERIAL COSI2 ON GAAS SUBSTRATES

The thermal stability of CoSi2 thin films on GaAs substrates has been studied using a variety of techniques. The CoSi2 thin films were formed by depositing Co(500 angstrom) and Si(1800 angstrom) layers on GaAs substrates by electron-beam evaporation followed by annealing processes, where the Si inter-layer was used as a diffusion/reaction barrier at the interface. The resistivity of CoSi2 thin films formed is about 30 muOMEGA cm. The Schottky barrier height of CoSi2/n-GaAs is 0.76 eV and the ideality factor is 1.14 after annealing at 750-degrees-C for 30 min. The CoSi2/GaAs interface is determined to be thermally stable and the thin film morphologically uniform on GaAs after 900-degrees-C/30 s anneal. The CoSi2 thin films fulfill the requirements in GaAs self-aligned gate technology.

INTERFACIAL REACTIONS IN THE CO/SI/GAAS AND SI/CO/GAAS SYSTEMS

The interfacial reactions between thin films of cobalt and silicon and (100)-oriented GaAs substrates in two configurations, Co/Si/GaAs and Si/Co/GaAs, were studied using a variety of techniques including Auger electron spectroscopy, x-ray diffraction, and transmission electron microscopy. The annealing conditions were 200, 300, 400, 600-degrees-C for 30 min, and rapid thermal annealing for 15 s. It was found that Si layer in the Co/Si/GaAs system acts as a barrier at the interface between Co and GaAs when annealed up to 600-degrees-C. The interfacial reaction between Co and Si is faster than that between Co and GaAs in the system of Si/Co/GaAs. The sequence of compound formation for the two metallizations studied (Co/Si/GaAs and Si/Co/GaAs) depends strongly on the sample configuration as well as the layer thickness of Si and Co (Co/Si atomic ratio). From our results, it is promising to utilize Co/Si/GaAs multilayer film structure to make a CoSi2/GaAs contact, and this CoSi2 may offer an alternative to the commonly used W silicides as improved gate metallurgies in self-aligned metal-semiconductor field effect transistor (MESFET) technologies.

A NEW METHOD FOR MEASURING THE EFFECTIVE DIFFUSION CONSTANT OF 2-DIMENSIONAL ELECTRONS IN THE PRESENCE OF MAGNETIC-FIELDS

The transient charge response Q(t) of a two-dimensional electron gas (2DEG) in GaAs/AlxGa1-xAs heterostructures to a small pulse of the gate voltage, applied between the top gate and source electrodes in a Corbino structure, was employed to directly measure the effective diffusion constant of a 2DEG in the quantum Hall regime. The measured diffusion constant D showed a drastic change as the magnetic field was swept through the integer fillings of the Landau levels.

1ST-PRINCIPLES CALCULATIONS FOR QUASI-PARTICLE ENERGIES OF GAP AND GAAS

We have applied the Green-function method in the GW approximation to calculate quasiparticle energies for the semiconductors GaP and GaAs. Good agreement between the calculated excitation energies and the experimental results was achieved. We obtained calculated direct band gaps of GaP and GaAs of 2.93 and 1.42 eV, respectively, in comparison with the experimental values of 2.90 and 1.52 eV, respectively. An ab initio pseudopotential method has been used to generate basis wave functions and charge densities for calculating the dielectric matrix elements and self-enegies. To evaluate the dynamical effects of the screened interaction, the generalized-plasma-pole model has been utilized to extend the dielectric matrix elements from static results to finite frequencies. We presen the calculated quasiparticle energies at various high-symmetry points of the Brillouin zone and compare them with the experimental results and other calculations.