Monolithically integrated semiconductor optical amplifier and electroabsorption modulator with dual-waveguide spot-size converter input and output

We have demonstrated an electroabsorption modulator and semiconductor optical amplifier monolithically integrated with novel dual-waveguide spot-size converters (SSC) at the input and output ports for low-loss coupling to a planar light-guide circuit silica waveguide or cleaved single-mode optical fibre. The device was fabricated by means of selective-area MOVPE growth, quantum well intermixing and asymmetric twin waveguide technologies with only a three-step low-pressure MOVPE growth. For the device structure, in the SOA/EAM section, a double ridge structure was employed to reduce the EAM capacitances and enable high bit-rate operation. In the SSC sections, buried ridge structure (BRS) was incorporated. Such a combination of ridge, ATG and BRS structure is reported for the first time in which it can take advantage of easy processing of the ridge structure and the excellent mode characteristic of BRS. At the wavelength range of 1550-1600 nm, lossless operation with extinction ratios of 25 dB dc and more than 10 GHz 3 dB bandwidth is successfully achieved, The beam divergence angles of the input and output ports of the device are as small as 8.0 degrees x 12.6 degrees, resulting in 3.0 dB coupling loss with a cleaved single-mode optical fibre.

Analysis of chirp characteristics of DFB lasers and integrated laser-modulators

A new method of analyzing the chirp characteristics of directly modulated lasers and integrated laser-modulators is presented in this paper. Phase-circuit has been introduced into the circuit model of distributed feedback (DFB) lasers in the analysis. Therefore, the chirp characteristics of the device can be obtained by simulating the modified circuit model. The simulation results agree well with the published data. Furthermore, this modified model is combined with the circuit model of electroabsorption (EA) modulators to simulate the chirp characteristics of the monolithic integration of a DFB laser and an EA modulator. The simulation is focused on the dependence of the frequency chirp of the integrated device on the isolation resistance between laser and modulator. Much lower chirp can be seen in the integrated lightwave source compared to the directly modulated laser.

Electrical and optical coupling in an electroabsorption modulator integrated with a DFB laser

Electrical and optical coupling in an electroabsorption (EA) modulator integrated with a distributed feedback (DFB) laser have been investigated. The integrated device is treated as a three-port optoelectronic device with two electrical ports and one optical output port. The scattering parameters of this three-port device have been measured in the designed experiment. The measured results indicate that there exists the electrical coupling between the DFB laser and EA modulator of the integrated light source whenever the current applied to the laser section is below or above the threshold current, and the optical coupling will have stronger influence on the frequency responses than the electrical coupling when the bias current is above the threshold. A small-signal equivalent circuit model for the integrated device is established considering both the electrical and internal optical coupling. Experiments show that the equivalent circuit model is reasonable and the determined element values are correct. Based on the measurement and modeling, the influences of the electrical and optical coupling on the high-frequency responses are investigated and the effective measure to eliminate the additional modulation in the DFB laser are discussed.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Electroabsorption modulated semiconductor optical amplifier monolithically integrated with spot-size converters

We have demonstrated an electroabsorption modulator (EAM) and semiconductor optical amplifier (SOA) monolithically integrated with novel dual-waveguide spot-size converters (SSCs) at the input and output ports for low-loss coupling to planar light-guide circuit silica waveguide or cleaved single-mode optical fiber. The device is fabricated by means of selective-area MOVPE growth (SAG), quantum well intermixing (QWI) and asymmetric twin waveguide (ATG) technologies with only three steps low-pressure MOVPE growth. For the device structure, in SOA/EAM section, double ridge structure was employed to reduce the EAM capacitances and enable high bit-rate operation. In the SSC sections, buried ridge stripe (BRS) were incorporated. Such a combination of ridge, ATG and BRS structure is reported for the first time in which it can take advantage of both easy processing of ridge structure and the excellent mode characteristic of BRS. At the wavelength range of 1550-1600 nm, lossless operation with extinction ratios of 25 dB DC and more than 10 GHz 3-dB bandwidth is successfully achieved. The beam divergence angles of the input and output ports of the device are as small as 8.0 degrees x 12.6 degrees, resulting in 3.0 dB coupling loss with cleaved single-mode optical fiber. (c) 2005 Elsevier B.V. All rights reserved.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Low Power Integrated Circuits for Wireless Neural Recording Applications

A group of prototype integrated circuits are presented for a wireless neural recording micro-system. An inductive link was built for transcutaneous wireless power transfer and data transmission. Power and data were transmitted by a pair of coils on a same carrier frequency. The integrated receiver circuitry was composed of a full-wave bridge rectifier, a voltage regulator, a date recovery circuit, a clock recovery circuit and a power detector. The amplifiers were designed with a limited bandwidth for neural signals acquisition. An integrated FM transmitter was used to transmit the extracted neural signals to external equipments. 16.5 mW power and 50 bps - 2.5 Kbps command data can be received over 1 MHz carrier within 10 mm. The total gain of 60 dB was obtained by the preamplifier and a main amplifier at 0.95Hz - 13.41 KHz with 0.215 mW power dissipation. The power consumption of the 100 MHz ASK transmitter is 0.374 mW. All the integrated circuits operated under a 3.3 V power supply except the voltage regulator.

An integrated optical receiver in MS/RF CMOS process

A monolithically integrated optoelectronic receiver was realized utilizing a deep sub-micron MS/RF CMOS process. Novel photo-diode with STI and highspeed receiver circuit were designed. This OEIC takes advantage of several new features to improve the performance.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

Simulation of a monolithically integrated CMOS bioamplifier for EEG recordings

A monolithically integrated CMOS bioamplifier is presented in this paper for EEG recording applications. The capacitive-coupled circuit input structure is utilized to eliminate the large and random DC offsets existing in the electrode-tissue interface. Diode-connected NMOS transistors with negative voltage between gate and source are candidates for large resistors necessary to the bioamplifier. A passive BEF (Band Eliminator Filter) can reduce 50 Hz noise disturbance strength by more than 60 dB. A novel analysis approach is given to help determine the noise power spectral density. Simulation results show that the two-stage CMOS bioamplifier in a closed-loop capacitive feedback configuration,provides an AC in-band gain of 39.6 dB, a DC gain of zero, and an input-referred noise of 87 nVrms integrated from 0.01 Hz to 100 Hz.

A CMOS front-end circuit for SONET OC-96 receiver

An optical receiver front-end for SONET OC-96 receivers was analyzed and designed in 0.18 mu m CMOS process. It consists of a transimpedance amplifier (TIA) and a limiting amplifier (LA). The TIA takes a fully differential configuration, and regulated cascode (RGC) input stage is implemented. The LA was realized by five cascaded identical gain stages with active inductor load. The TIA achieved 4.2GHz bandwidth for 0.5pF photodiode (PD) capacitance and 1.2k 0 transimpedance gain. The LA achieved 5.4GHz bandwidth and 29dB voltage gain. The optical sensitivity is -19dBm at 5-Gb/s for a bit-error rate of 10(-12), and it dissipates 45.5mW for I.8V supply.

A novel fast lock-in phase-locked loop frequency synthesizer with direct frequency presetting circuit

This paper proposes a novel, fast lock-in, phase-locked loop (PLL) frequency synthesizer. The synthesizer includes a novel mixed-signal voltage-controlled oscillator (VCO) with a direct frequency presetting circuit. The frequency presetting circuit can greatly speed up the lock-in process by accurately the presetting oscillation frequency of the VCO. We fully integrated the synthesizer in standard 0.35 mu m, 3.3 V complementary metal-oxide-semiconductors (CMOS) process. The entire chip area is only 0.4 mm(2). The measured results demonstrate that the synthesizer can speed up the lock-in process significantly and the lock-in time is less than 10 mu s over the entire oscillation frequency range. The measured phase noise of the synthesizer is -85 dBc/Hz at 10 kHz offset. The synthesizer avoids the tradeoff between the lock-in speed and the phase noise/spurs. The synthesizer monitors the chip temperature and automatically compensates for the variation in frequency with temperature.

Electroabsorption modulated semiconductor optical amplifier monolithically integrated with spot-size converters

We have demonstrated an electroabsorption modulator (EAM) and semiconductor optical amplifier (SOA) monolithically integrated with novel dual-waveguide spot-size converters (SSCs) at the input and output ports for low-loss coupling to planar light-guide circuit silica waveguide or cleaved single-mode optical fiber. The device is fabricated by means of selective-area MOVPE growth (SAG), quantum well intermixing (QWI) and asymmetric twin waveguide (ATG) technologies with only three steps low-pressure MOVPE growth. For the device structure, in SOA/EAM section, double ridge structure was employed to reduce the EAM capacitances and enable high bit-rate operation. In the SSC sections, buried ridge stripe (BRS) were incorporated. Such a combination of ridge, ATG and BRS structure is reported for the first time in which it can take advantage of both easy processing of ridge structure and the excellent mode characteristic of BRS. At the wavelength range of 1550-1600 nm, lossless operation with extinction ratios of 25 dB DC and more than 10 GHz 3-dB bandwidth is successfully achieved. The beam divergence angles of the input and output ports of the device are as small as 8.0 degrees x 12.6 degrees, resulting in 3.0 dB coupling loss with cleaved single-mode optical fiber. (c) 2005 Elsevier B.V. All rights reserved.

A simulation model of body contact structure in PD SOI analogue circuit

As a solution of accurate simulation of the body effect in PD SOI analogue circuit, a simulation model of distributed body contact resistance and parasitical capacitance is presented. Based on this model, we have designed and simulated a sense amplifier that applied to V a 0.8um PD SOI 64K SRAM.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.