Compensatory growth in the gibel carp following feed deprivation: temporal patterns in growth, nutrient deposition, feed intake and body composition

To investigate the nature of compenstory growth in fish, an 8 week study at 28 degreesC was performed on juvenile gibel carp Carassius auratus gibelio weighing 6.6 g. Fish were starved for 0 (control), 1 (Sl)or 2 (S2) weeks and then re-fed to satiation For 5 weeks. Weekly changes in weight gain, feed intake and body composition were monitored during re-feeding. No significant difference was found in final body weight between the three groups, indicating complete compensation in the deprived fish, The deprived groups caught up in body weight with that of the control after 2 weeks of re-feeding. Body fat:lean body mass ratio was restored to the control level within 1 week of re-feeding. In the re-feeding period, weekly gains in body weight, protein. lipid, ash and energy in the S1 group were significantly higher than in the controls for 1 week. For the S2 group, weekly gains in body weight. lipid. ash and energy were higher than in the controls for 2 weeks, and gain in protein was higher than in the controls for 3 weeks, though gain in body energy became elevated again during the last 2 weeks of the experiment. Feed intake remained higher than the control level for 3 weeks in the S1 group and 3 weeks in the SZ group. Growth efficiency was not significantly different among the three groups in any of the weeks during re-feeding. Compensatory responses in growth and especially feed intake tended to last longer than the recovery of body composition. (C) 2001 The Fisheries Society of the British Isles.

Compact Reconfigurable Binary-Decision-Diagram Logic Circuit on a GaAs Nanowire Network

We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated.

FREQUENCY AND TEMPORAL COHERENCE PROPERTIES OF DISTRIBUTED BRAGG REFLECTOR LASER

This article presents the investigation of frequency and temporal coherence properties of distributed Bragg reflector laser. In this scheme, a square-wavefrom voltage is applied to the phase section of the laser to little optical wavelength, and delayed optical heterodyne technique is used for the analysis of spectral characteristics. Experiments show that lightwaves emitted from the same active region asynchronously are partially frequency and temporal coherent. When the two wavelengths are closer, the two waves are strong v coherent, and the coherence properties get weak as the delay v time increases. (C) 2010 Wiley Periodicals, Inc. Microwave Opt Technol Left 52: 822-825, 2010 Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25031

Smart universal multiple-valued logic gates by transferring single electrons

This paper proposes smart universal multiple-valued (MV) logic gates by transferring single electrons (SEs). The logic gates are based on MOSFET based SE turnstiles that can accurately transfer SEs with high speed at high temperature. The number of electrons transferred per cycle by the SE turnstile is a quantized function of its gate voltage, and this characteristic is fully exploited to compactly finish MV logic operations. First, we build arbitrary MV literal gates by using pairs of SE turnstiles. Then, we propose universal MV logic-to-value conversion gates and MV analog-digital conversion circuits. We propose a SPICE model to describe the behavior of the MOSFET based SE turnstile. We simulate the performances of the proposed gates. The MV logic gates have small number of transistors and low power dissipations.

Compact universal logic gates realized using quantization of current in nanodevices

This paper proposes novel universal logic gates using the current quantization characteristics of nanodevices. In nanodevices like the electron waveguide (EW) and single-electron (SE) turnstile, the channel current is a staircase quantized function of its control voltage. We use this unique characteristic to compactly realize Boolean functions. First we present the concept of the periodic-threshold threshold logic gate (PTTG), and we build a compact PTTG using EW and SE turnstiles. We show that an arbitrary three-input Boolean function can be realized with a single PTTG, and an arbitrary four-input Boolean function can be realized by using two PTTGs. We then use one PTTG to build a universal programmable two-input logic gate which can be used to realize all two-input Boolean functions. We also build a programmable three-input logic gate by using one PTTG. Compared with linear threshold logic gates, with the PTTG one can build digital circuits more compactly. The proposed PTTGs are promising for future smart nanoscale digital system use.

Photonic switch and NOT logic gate based on the hybrid integration of a GaAsVCSEL and a GaAs MISS

The hybrid integrated photonic switch and not logic gate based on the integration of a GaAs VCSEL (Vertical Cavity Surface Emitting Lasers) and a MISS (Metal-Insulator-Semiconductor Switches) device are reported. The GaAs VCSEL is fabricated by selective etching and selective oxidation. The Ultra-Thin semi-Insulating layer (UTI) of the GaAs MISS is formed by using oxidation of A1As that is grown by MBE. The accurate control of UTI and the processing compatibility between VCSEL and MISS are solved by this procedure. Ifa VCSEL is connected in series with a MISS, the integrated device can be used as a photonic switch, or a light amplifier. A low switching power (10 mu W) and a good on-off ratio (17 dB contrast) have been achieved. If they are connected in parallel, they perform a photonic NOT gate operation.

Electro-optical properties and temporal stability of the guest-host DCNP/PEK-c polymer thin film

The polyetherketone (PEK-c) guest-host system thin films in which the range of the weight percent of 3-(1,1-dicyanothenyl)-1-phenyl-4, 5- dihydro-1H-pryazole (DCNP) is from 20% to 50% were prepared. The predicted high value of electro-optical (EO) coefficient gamma(33) = 48.8 pm/V by using two-level model was obtained when the weight percent of DCNP in the polymer system is 40%, whereas EO coefficients are attenuated at higher chromophore loading then 40%. The temporal stability of the EO activity of the guest-host polymer was evaluated by probing the decay of the orientational order of the chromophores in the polymer system.

Monostable-Bistable Transition Logic Element (MOBILE) Model for Single-Electron Transistors

The traditional monostable-bistable transition logic element (MOBILE) structure is usually composed of resonant tunneling diodes (RTD). This letter describes a new type MOBILE structure consisting of single-electron transistors (i.e. SET-MOBILE). The analytical model of single-electron transistors ( SET) has been considered three states (including an excited state) of the discrete quantum energy levels. The simulation results show negative differential conductance (NDC) characteristics in I-DS-V-DS curve. The SET-MOBILE utilizing NDC characteristics can successfully realize the basic logic functions as the RTD-MOBILE.

An Embedded Ultra Low Power Nonvolatile Memory in a Standard CMOS Logic Process

This paper proposes an embedded ultra low power nonvolatile memory in a standard CMOS logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mu m 1P4M standard CMOS logic process and the core area is 0.06 mm(2). The measured results indicate that the typical write/erase time is 10ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 mu A for program and 1.2 mu A for read at a 1.6V power supply.

Demonstration of directed XOR/XNOR logic gates using two cascaded microring resonators

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A logic for default reasoning

The need to make default assumptions is frequently encountered in reasoning about incompletely specified worlds. Inferences sanctioned by default are best viewed as beliefs which may well be modified or rejected by subsequent observations. It is this property which leads to the non-monotonicity of any logic of defaults. In this paper we propose a logic for default reasoning. We then specialize our treatment to a very large class of commonly occuring defaults. For this class we develop a complete proof theory and show how to interface it with a top down resolution theorem prover. Finally, we provide criteria under which the revision of derived beliefs must be effected.