98 resultados para Noise-tolerance
Resumo:
Based on our recent work on quantum transport [X. Q. Li , Phys. Rev. B 71, 205304 (2005)], we show how an efficient calculation can be performed for the current noise spectrum. Compared to the classical rate equation or the quantum trajectory method, the proposed approach is capable of tackling both the many-body Coulomb interaction and quantum coherence on an equal footing. The practical applications are illustrated by transport through quantum dots. We find that this alternative approach is in a certain sense simpler and more straightforward than the well-known Landauer-Buttiker scattering matrix theory.
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This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.
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National Natural Science Foundation of China 10674129
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This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.
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Size tolerance of a 4X4 general interference tapered multimode interference (MMI) coupler in a silicon-on-insulator (SOI) structure is investigated by means of a 2-D finite difference beam propagation method (2D-FDBPM), together with an effective refractive index method (EIM). The results show that the tapered multimode interference coupler exhibits relatively larger size tolerance when light is launched from the edgeport than from midport, though it has much better output power uniformity when light is launched from midport. Besides that, it can reduce the device length greatly. The 4X4 general interference tapered MMI coupler has a slightly larger size tolerance compared with a conventional straight multimode interference coupler. (C) 2003 Society of Photo-Optical Instrumentation Engineers.
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We have investigated random telegraph noise in the photoluminescence from InGaAs quantum dots in GaAs. Dots switching among two and three levels have been measured. The experiments show that the switching InGaAs dots behave very similarly to switching InP dots in GaInP. but differently from the more commonly investigated colloidal dots. The switching is attributed to defects, and we show that the switching can be used as a monitor of the defect.
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We demonstrate a type of 2 x 2 multimode interference 3 dB coupler based on silicon-on-insulator. The fabrication tolerance was investigated by the effective index method and the guide mode method. The devices with different lengths were fabricated and near-held output images were obtained. Tolerances to width, length and etch depth are 2, 200 and 2 mum, respectively. The devices show a uniform power distribution.
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We report experiments on hot-electron stressing in commercial III-V nitride based heterojunction fight-emitting diodes. Stressing currents ranging from 100 mA to 200 mA were used. Degradations in the device properties were investigated through detailed studies of the I-V characteristics, electroluminescence, Deep-Level Transient Fourier Spectroscopy and flicker noise. Our experimental data demonstrated significant distortions in the I-V characteristics. The room temperature electroluminescence of the devices exhibited 25% decrement in the peak emission intensity. Concentration of the deep-levels was examined by measuring the Deep-Level Transient Fourier Spectroscopy, which indicated an increase in the density of deep-traps from 2.7 x 10(13) cm(-3) to 4.21 x 10(13) cm(-3) at E-1 = E-C - 1.1eV. The result is consistent with our study of 1/f noise, which exhibited up to three orders of magnitude increase in the voltage noise power spectra. Our experiments show large increase in both the interface traps and deep-levels resulted from hot-carrier stressing.
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This paper presents the design of a wide-band low-noise amplifier (LNA) implemented in a 0.35 mu m SiGe BiCMOS technology for cable (DVB-C) and terrestrial (DVB-T) tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure(NF) of the wideband LNA is 5dB, its 1-dB compression point is -2dBm and IIP3 is 8dBm. The LNA dissipates 120mW power with a 5-V supply.
Resumo:
This paper presents a direct digital frequency synthesizer (DDFS) with a 16-bit accumulator, a fourth-order phase domain single-stage Delta Sigma interpolator, and a 300-MS/s 12-bit current-steering DAC based on the Q(2) Random Walk switching scheme. The Delta Sigma interpolator is used to reduce the phase truncation error and the ROM size. The implemented fourth-order single-stage Delta Sigma noise shaper reduces the effective phase bits by four and reduces the ROM size by 16 times. The DDFS prototype is fabricated in a 0.35-mu m CMOS technology with active area of 1.11 mm(2) including a 12-bit DAC. The measured DDFS spurious-free dynamic range (SFDR) is greater than 78 dB using a reduced ROM with 8-bit phase, 12-bit amplitude resolution and a size of 0.09 mm(2). The total power consumption of the DDFS is 200)mW with a 3.3-V power supply.
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This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.
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A novel type of interferometer, the moving-mirror-pair interferometer, is presented, and its principle and properties are studied. The new interferometer is built with three flat mirrors, which include two flat moving mirrors fixed as a single moving part by a rigid structure and one flat fixed mirror. The optical path difference (OPD) is obtained by the straight reciprocating motion of the double moving mirror, and the OPD value is four times the physical shift value of the double moving mirror. The tilt tolerance of the double moving mirror of the novel interferometer is systematically analyzed by means of modulation depth and phase error. Where the square aperture is concerned, the formulas of the tilt tolerance were derived. Due to the novel interferometer's large OPD value and low cost, it is very applicable to the high-spectral-resolution Fourier-transform spectrometers for any wavenumber region from the far infrared to the ultraviolet. (C) 2008 Optical Society of America.
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This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.
Resumo:
We present the design of a wide-band low-noise amplifier (LNA) implemented in 0.35μm SiGe BiCMOS technology for cable and terrestrial tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1 ~ 1GHz wide bandwidth and 18. 8dB gain with less than 1.4dB of gain variation. The noise figure of the wideband LNA is 5dB, and its 1dB compression point is - 2dBm and IIP3 is 8dBm. The LNA dissipates 120mW of power with a 5V supply.