Novel folding 8x8 silicon-based optical matrix switch with tapered waveguides and self-aligned corner mirrors

Novel folding 8 x 8 matrix switches based on silicon on insulator were demonstrated. In the design, single-mode rib waveguides and multimode interferences are connected by optimized tapered waveguides to reduce the mode coupling loss between the two types of waveguides. The self-aligned method was applied to the key integrated turning mirrors for perfect positions and low loss of them. A mixed etching process including inductively coupled plasma and chemical etching was employed to etch waveguides and mirrors, respectively. The compact size of the device is only 20 x 3.2 mm(2). The switch element with high switching speed and low power consumption is presented in the matrix. The average insertion loss of the matrix is about -21 dB, and the excess loss of one mirror is measured of -1.4 dB. The worst crosstalk is larger than 21 dB. Experimental results illuminate that some of the main characteristics of optical matrix switches are. developed in the modified design, which is in accord with theoretic analyses.

Anti-Stokes photoluminescence in ZnO microcrystal

Low temperature (10 K) strong anti-Stokes photoluminescence (ASPL) of ZnO microcrystal excited by low power cw 532 nm laser is reported here. Energy upconversion of 1.1 eV is obtained in our experiment with no conventional nonlinear effect. Through the study of the normal photoluminescence and temperature dependence of ASPL we conclude that the green band luminescence in ZnO is related to deep donor to valance band transition. Using the two-step two-photon absorption model, we provide a plausible mechanism leading to the ASPL phenomenon in our experiment. (c) 2006 American Institute of Physics.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Simulation of single electronic device and robust circuit construction

The article mainly focuses on the simulation of the single electron device and circuit. The orthodox model of single electronic device is introduced and the simulation with Matlab and Pspice is illustrated in the article. Moreover, the built of robust circuit using single electronic according to neural network is done and the simulation is also included in the paper. The result shows that neural network added with proper redundancy is an available candidate for single electron device circuit. The proposed structure is also promising for the realization of low ultra-low power consumption and solution of transient device failure.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

Recent progresses of silicon-based optoelectronic devices for application in fiber communication

Si-based optoelectronic devices, including stimulated emission from Si diode, 1.3 and 1.5mum SiGe photodetector with quantum structures, 1GHz MOS optical modulator, SOI optical switch matrix and wavelength tunable filter are reviewed in the paper.

A 10 Gb/s Directly-Modulated 1.3 mu m InAs/GaAs Quantum-Dot Laser

We demonstrate 10 Gb/s directly-modulated 1.3 mu m InAs quantum-dot (QD) lasers grown on GaAs substrates by molecular beam epitaxy. The active region of the QD lasers consists of five-stacked InAs QD layers. Ridge-waveguide lasers with a ridge width of 4 mu m and a cavity length of 600 mu m are fabricated with standard lithography and wet etching techniques. It is found that the lasers emit at 1293 nm with a very low threshold current of 5 mA at room temperature. Furthermore, clear eye-opening patterns under 10 Gb/s modulation rate at temperatures of up to 50 degrees C are achieved by the QD lasers. The results presented here have important implications for realizing low-cost, low-power-consumption, and high-speed light sources for next-generation communication systems.

A novel noise optimization technique for inductively degenerated CMOS LNA

This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

A multi-standard active-RC filter with accurate tuning system

A low-power, highly linear, multi-standard, active-RC filter with an accurate and novel tuning architec-ture is presented. It exhibits 1EEE 802. 11a/b/g (9.5 MHz) and DVB-H (3 MHz, 4 MHz) application. The filter exploits digitally-controlled polysilicon resistor banks and a phase lock loop type automatic tuning system. The novel and complex automatic frequency calibration scheme provides better than 4 comer frequency accuracy, and it can be powered down after calibration to save power and avoid digital signal interference. The filter achieves OIP3 of 26 dBm and the measured group delay variation of the receiver filter is 50 ns (WLAN mode). Its dissipation is 3.4 mA in RX mode and 2.3 mA (only for one path) in TX mode from a 2.85 V supply. The dissipation of calibration consumes 2 mA. The circuit has been fabricated in a 0.35μm 47 GHz SiGe BiCMOS technology; the receiver and transmitter filter occupy 0.21 mm~2 and 0.11 mm~2 (calibration circuit excluded), respectively.

A Compact Direct Digital Frequency Synthesizer for the Rubidium Atomic Frequency Standard

A compact direct digital frequency synthesizer （DDFS） for system-on-chip implementation of the high precision rubidium atomic frequency standard is developed. For small chip size and low power consumption, the phase to sine mapping data is compressed using sine symmetry technique, sine-phase difference technique, quad line approximation technique,and quantization and error read only memory （QE-ROM） technique. The ROM size is reduced by 98% using these techniques. A compact DDFS chip with 32bit phase storage depth and a 10bit on-chip digital to analog converter has been successfully implemented using a standard 0.35μm CMOS process. The core area of the DDFS is 1.6mm^2. It consumes 167mW at 3.3V,and its spurious free dynamic range is 61dB.

低功率氩电弧加热发动机的数值模拟

采用可求解可压缩流动与传热的全速度SIMPLE算法, 对低功率氩电弧加热发动机内部的传热与流动进行了数值模拟, 获得了电弧加热发动机内的温度、速度、马赫数及流线分布. 计算结果表明: 电弧加热发动机内最高温度出现在阴极下游附近中心轴线处, 这是因为电弧在阴极表面收缩形成阴极弧点, 从而焦耳热成为该高温区的主要加热机制; 沿着发动机中心轴线, 气体温度和速度开始时随着距阴极距离的增加而迅速增加, 然后在等离子体流向喷管出口的过程中, 气体温度和速度逐渐下降. 此外还详细考察了弧电流变化对电弧加热发动机内部传热与流动特性的影响, 计算获得的发动机流量和比冲与实验结果基本一致.

基于MSP430 单片机和DS18B20 的多分支多通道温度测量系统远程监控软件

This paper present that the system can acquire the remote temperature measurement data of 40 monitoring points,through the RS-232 serial port and the Intranet.System s hardware is consist of TI s MSP430F149 mixed-signal processor and UA7000A network module.Using digital temperature sensor DS18B20,the structure is simple and easy to expand,the sensors directly send out the temperature data.MSP430F149 has the advantage of ultra-low-power and high degree of integration.Using msp430F149,the multi-branch multi-p...中文文摘：文章论述了通过RS-232串口和Intranet网络,来实现对远端的40个温度测量点的监控。系统硬件由TI公司的MSP430F149混合信号处理器和UA7000A网络模块构成。传感器采用数字式温度传感器DS18B20,它将直接得到温度的数字量,结构简单,易于扩展。MSP430F149处理器具有超低功耗和高度集成等优点,利用它构建的多分支多通道温度测量系统功能强大,结构简单,可靠性高,抗干扰能力强。系统客户端软件采用Microsoft Visual C++6.0设计。本监控系统能够很好地完成对4个分支共40个温度测量点的远程实时监控。

基于TCP/ IP 协议的CSR离子泵电源远程监控软件系统设计

This paper discuss a Ion-pump Power Supply control system making use of RS232 series bus and Intranet.The system s hardware VAC800 is composed of MSP430F149 mixed-signal processors produced by TI and UA7000A network model.MSP430F149 has advantages of ultra-low-power and high-integration.The Ion-pump Power Supply control system has the characteristics of strong function,simple structure,high reliability,strong resistance of noise,no peripheral chip,etc.Visual studio 2005 is used to design the system s softwa...中文文摘：论述了通过RS-232总线和Intranet网络,来实现对远端的离子泵电源的监测与控制。系统硬件VAC800由TI公司的MSP430F149混合信号处理器和UA7000A网络模块构成。MSP430F149具有超低功耗和高集成度等优点,利用它构建的离子泵电源监控系统功能强大,结构简单,可靠性高,抗干扰能力强。系统软件采用visual studio 2005设计。本监控系统能够很好地完成对加速器离子泵电源监视与控制。

ECC密码算法的低功耗硬件实现研究

椭圆曲线密码算法作为高安全性的公钥密码;ECC算法的优化和软硬件实现是当前的研究热点;采用硬件实现椭圆曲线密码算法具有速度快、安全性高的特点,随着功耗分析、旁路攻击等新型分析方法的发展,密码算法硬件实现中的低功耗设计越来越重要;针对椭圆曲线密码算法的特点,主要对该算法芯片设计中的低功耗设计方法进行探讨。

Negative differential resistance effect in organic devices based on an anthracene derivative

The authors observed a negative differential resistance (NDR) in organic devices consisting of 9,10-bis-(9,9-diphenyl-9H-fluoren-2-yl)-anthracene (DPFA) sandwiched between Ag and indium tin oxide electrodes. The large NDR shown in current-voltage characteristics is reproducible, resulting in that the organic devices can be electrically switched between a high conductance state (on state) and a low conductance state (off state). It can be found that the currents at both on to off states are space-charge limited and attributed to the electron traps at the Ag/DPFA interface. The large and reproducible NDR makes the devices of tremendous potential in low power memory and logic circuits.