A Fully Integrated 900-MHz Passive RFID Transponder Front End With Novel Zero-Threshold RF-DC Rectifier

This paper presents a fully integrated CMOS analog front end for a passive 900-MHz radio-frequency identification (RFID) transponder. The power supply in this front end is generated from the received RF electromagnetic energy by using an RF-dc voltage rectifier. In order to improve the compatibility with standard CMOS technology, Schottky diodes in conventional RF-dc rectifiers are replaced by diode-connected MOS transistors with zero threshold. Meanwhile, theoretical analyses for the proposed rectifier are provided and verified by both simulation and measurement results. The design considerations of the pulsewidth-modulation (PWM) demodulator and the backscatter modulator in the front end are also discussed for low-power applications. The proposed front end is implemented in a 0.35-mu m 2P4M CMOS technology. The whole chip occupies a die area of 490 x 780 mu m(2) and consumes only 2.1 mu W in reading mode under a self-generated 1.5-V supply voltage. The measurement results show that the proposed rectifier can properly operate with a - 14.7-dBm input RF power at a power conversion efficiency of 13.0%. In the proposed RFID applications, this sensitivity corresponds to 10.88-m communication distance at 4-W equivalent isotropically radiated power from a reader base station.

Novel folding large-scale optical switch matrix with total internal reflection mirrors on silicon-on-insulator by anisotropy chemical etching

A compact optical switch matrix was designed, in which light circuits were folded by total internal reflective (TIR) mirrors. Two key elements, 2 x 2 switch and TIR mirror, have been fabricated on silicon-on-insulator wafer by anisotropy chemical etching. The 2 x 2 switch showed very low power consumption of 140 mW and a very high speed of 8 +/- 1 mus. An improved design for the TIR mirror was developed, and the fabricated mirror with smooth and vertical reflective facet showed low excess loss of 0.7 +/- 0.3 dB at 1.55 mum.

Mode analysis and Q-factor enhancement due to mode coupling in rectangular resonators

Modes in rectangular resonators are analyzed and classified according to symmetry properties, and quality factor (Q-factor) enhancement due to mode coupling is observed. In the analysis, mode numbers p and q are used to denote the number of wave nodes in the direction of two orthogonal sides. The even and odd mode numbers correspond to symmetric and antisymmetric field distribution relative to the midlines of sides, respectively. Thus, the modes in a rectangle resonator can be divided into four classes according to the parity of p and q. Mode coupling between modes of different classes is forbidden; however, anti-crossing mode coupling between the modes in the same class exists and results in new modes due to the combination of the coupled modes. One of the combined modes has very low power loss and high Q-factor based on far-field emission of the analytical field distribution, which agrees well with the numerical results of the finite-difference time-domain (FDTD) simulation. Both the analytical and FDTD results show that the Q-factors of the high Q-factor combined modes are over one order larger than those of the original modes. Furthermore, the general condition required to achieve high-Q modes in the rectangular resonator is given based on the analytical solution.

Novel hybrid voltage controlled ring oscillators using single electron and MOS transistors

This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.

Submicrosecond rearrangeable nonblocking silicon-on-insulator thermo-optic 4 X 4 switch matrix

A rearrangeable nonblocking silicon-on-insulator-based thermo-optic 4 X 4 switch matrix is designed and fabricated. A spot-size converter is integrated to reduce the insertion loss, and a new driving circuit is designed to improve the response speed. The insertion loss is less than 10 dB, and the response time is 950 us. (c) 2007 Optical Society of America

Novel folding 8x8 silicon-based optical matrix switch with tapered waveguides and self-aligned corner mirrors

Novel folding 8 x 8 matrix switches based on silicon on insulator were demonstrated. In the design, single-mode rib waveguides and multimode interferences are connected by optimized tapered waveguides to reduce the mode coupling loss between the two types of waveguides. The self-aligned method was applied to the key integrated turning mirrors for perfect positions and low loss of them. A mixed etching process including inductively coupled plasma and chemical etching was employed to etch waveguides and mirrors, respectively. The compact size of the device is only 20 x 3.2 mm(2). The switch element with high switching speed and low power consumption is presented in the matrix. The average insertion loss of the matrix is about -21 dB, and the excess loss of one mirror is measured of -1.4 dB. The worst crosstalk is larger than 21 dB. Experimental results illuminate that some of the main characteristics of optical matrix switches are. developed in the modified design, which is in accord with theoretic analyses.

Anti-Stokes photoluminescence in ZnO microcrystal

Low temperature (10 K) strong anti-Stokes photoluminescence (ASPL) of ZnO microcrystal excited by low power cw 532 nm laser is reported here. Energy upconversion of 1.1 eV is obtained in our experiment with no conventional nonlinear effect. Through the study of the normal photoluminescence and temperature dependence of ASPL we conclude that the green band luminescence in ZnO is related to deep donor to valance band transition. Using the two-step two-photon absorption model, we provide a plausible mechanism leading to the ASPL phenomenon in our experiment. (c) 2006 American Institute of Physics.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Nanoelectronic Circuit Architectures Based on Single-Electron Turnstiles

Single-electron devices (SEDs) have ultra-low power dissipation and high integration density, which make them promising candidates as basic circuit elements of the next generation VLSI circuits. In this paper, we propose two novel circuit single-electron architectures: the single-electron simulated annealing algorithm (SAA) circuit and the single-electron cellular neural network (CNN). We used the MOSFET-based single-electron turnstile [1] as the basic circuit element. The SAA circuit consists of the voltage-controlled single-electron random number generator [2] and the single-electron multiple-valued memories (SEMVs) [3]. The random-number generation and variable variations in SAA are easily achieved by transferring electrons using the single-electron turnstile. The CNN circuit used the floating-gate single-electron turnstile as the neural synapses, and the number of electrons is used to represent the cells states. These novel circuits are promising in future nanoscale integrated circuits.

Simulation of single electronic device and robust circuit construction

The article mainly focuses on the simulation of the single electron device and circuit. The orthodox model of single electronic device is introduced and the simulation with Matlab and Pspice is illustrated in the article. Moreover, the built of robust circuit using single electronic according to neural network is done and the simulation is also included in the paper. The result shows that neural network added with proper redundancy is an available candidate for single electron device circuit. The proposed structure is also promising for the realization of low ultra-low power consumption and solution of transient device failure.

An 8-b 1-GSmaples/s CMOS cascaded folding and interpolating ADC

This paper presents an 8-bit low power cascaded folding and interpolating analog-to-digital converter (ADC). A reduction in the number of comparators, equal to the number of times the signal is folded, is obtained. The interleaved architecture is used to improve the sampling rate of the ADC. The circuit including a bandgap is implemented in a 0.18-mu m CMOS technology, and measures 1.47 mm X 1.47 mm (including pads). The simulation results illustrate a conversion rate of 1-GSamples/s and a power dissipation of less than 290mW.

A novel DC-DC charge pump circuit for passive RFID transponder

This paper presents a low-voltage, high performance charge pump circuit suitable for implementation in standard CMOS technologies. The proposed charge pump has been used as a part of the power supply section of fully integrated passive radio frequency identification(RFID) transponder IC, which has been implemented in a 0.35-um CMOS technology with embedded EEPROM offered by Chartered Semiconductor. The proposed DC/DC charge pump can generate stable output for RFID applications with low power dissipation and high pumping efficiency. The analytical model of the voltage multiplier, the comparison with other charge pumps, the simulation results, and the chip testing results are presented.

Recent progresses of silicon-based optoelectronic devices for application in fiber communication

Si-based optoelectronic devices, including stimulated emission from Si diode, 1.3 and 1.5mum SiGe photodetector with quantum structures, 1GHz MOS optical modulator, SOI optical switch matrix and wavelength tunable filter are reviewed in the paper.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

A 10 Gb/s Directly-Modulated 1.3 mu m InAs/GaAs Quantum-Dot Laser

We demonstrate 10 Gb/s directly-modulated 1.3 mu m InAs quantum-dot (QD) lasers grown on GaAs substrates by molecular beam epitaxy. The active region of the QD lasers consists of five-stacked InAs QD layers. Ridge-waveguide lasers with a ridge width of 4 mu m and a cavity length of 600 mu m are fabricated with standard lithography and wet etching techniques. It is found that the lasers emit at 1293 nm with a very low threshold current of 5 mA at room temperature. Furthermore, clear eye-opening patterns under 10 Gb/s modulation rate at temperatures of up to 50 degrees C are achieved by the QD lasers. The results presented here have important implications for realizing low-cost, low-power-consumption, and high-speed light sources for next-generation communication systems.