Silicon light emitting devices in CMOS technology

Two silicon light emitting devices with different structures are realized in standard 0.35 mu m complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6 nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/Cm-2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm..

XPS depth profiling study of n/TCO interfaces for p-i-n amorphous silicon solar cells

Detailed X-ray photoelectron spectroscopy (XPS) depth profiling measurements were performed across the back n-layer/transparent conducting oxide (n/TCO) inter-faces for superstrate p-i-n solar cells to examine differences between amorphous silicon (a-Si:H) and microcrystalline silicon (mu c-Si:H) n-layer materials as well as TCO materials ZnO and ITO in the chemical, microstructural and diffusion properties of the back interfaces. No chemical reduction of TCO was found for all variations of n-layer/TCO interfaces. We found that n-a-Si:H interfaces better with ITO, while n-mu c-Si:H, with ZnO. A cross-comparison shows that the n-a-Si:H/ITO interface is superior to the n-mu c-Si:H/ZnO interface, as evidenced by the absence of oxygen segregation and less oxidized Si atoms observed near the interface together with much less diffusion of TCO into the n-layer. The results suggest that the n/TCO interface properties are correlated with the characteristics of both the n-layer and the TCO layer. Combined with the results reported on the device performance using similar back n/TCO contacts, we found the overall device performance may depend on both interface and bulk effects related to the back n/TCO contacts. (c) 2006 Elsevier B.V. All rights reserved.

Synthesis and photoluminescence properties of vertically aligned ZnO nanorod-nanowall junction arrays on a ZnO-coated silicon substrate

Arrays of vertically well-aligned ZnO nanorod-nanowall junctions have been synthesized on an undoped ZnO-coated silicon substrate by a carbothermal reduction and vapour phase transport method. X-ray diffraction (XRD) and scanning electron microscopy (SEM) show that the nanostructures are well-oriented with the c-axis perpendicular to the substrate. The room temperature photoluminescence (PL) spectrum of the as-prepared ZnO nanostructure reveals a dominant near-band-edge (NBE) emission peak and a weak deep level (DL) emission, which demonstrates its good optical properties. Temperature-dependent PL spectra show that both the intensity of NBE and DL emissions increased with decreasing temperature. The NBE emission at 3.27 eV is identified to originate from the radiative free exciton recombination. The possible growth mechanism of ZnO nanorod-nanowall junctions is also proposed.

Electroluminescence afterglow from indium tin oxide/Si-rich SiO2/p-Si structure

Indium tin oxide/Si-rich SiO2/p-Si structured devices are fabricated to study the electroluminescence (EL) of the Si-rich SiO2 (SRO) material. The obvious peaks at similar to 1050nm and similar to 1260nm in the EL are ascribed to localized state transitions of amorphous Si (alpha-Si) clusters. The EL afterglow associated with alpha-Si clusters is observed from this structure at room temperature, while the afterglow is absent in the case of optical pumping. It is believed that carrier-induced defects act as trap centres in the alpha-Si clusters, resulting in the EL afterglow. The phenomenon of the EL afterglow indicates the limits of EL performance and electrical modulation of the SRO material with a larger fraction of alpha-Si clusters.

Amorphous silicon nanoparticles in compound films grown on cold substrates for high-efficiency photoluminescence

Silicon nanoparticles have been fabricated in both oxide and nitride matrices by using plasma-enhanced chemical vapour deposition, for which a low substrate temperature down to 50 degreesC turns out to be most favourable. High-rate deposition onto such a cold substrate results in the formation of nanoscaled silicon particles, which have revealed an amorphous nature under transmission electron microscope (TEM) examination. The particle size can be readily controlled below 3.0 nm, and the number density amounts to over 10(12) cm(-2), as calculated from the TEM micrographs. Strong photoluminescence in the whole visible light range has been observed in the as-deposited Si-in-SiOx and Si-in-SiNx thin films. Without altering the size or structure of the particles, a post-annealing at 300 degreesC for 2 min raised the photoluminescence efficiency to a level comparable to the achievements with nanocrystalline Si-in-SiO2 samples prepared at high temperature. This low-temperature procedure for fabricating light-emitting silicon structures opens up the possibility of manufacturing integrated silicon-based optoelectronics.

Photoluminescence behaviors from stoichiometric gadolinium oxide films

Stoichiometric gadolinium oxide thin films have been grown on silicon (100) substrates with a low-energy dual ion-beam epitaxial technique. Gadolinium oxide shares Gd2O3 structures although the ratio of gadolinium and oxygen in the film is about 2:1 and a lot of oxygen deficiencies exist. Photoluminescence (PL) measurements have been carried out within a temperature range of 5-300 K. The detailed characters of the PL emission integrated intensity, peak position, and peak width at different temperature were reported and an anomalous photoluminescence behavior was observed. The character of PL emission integrated intensity is similar to that of some other materials such as porous silicon and silicon nanocrystals in silicon dioxide. Four peaks relative to alpha band and beta band were observed also. Therefore we suggest that the nanoclusters with the oxygen deficiencies contribute to the PL emission and the model of singlet-triplet exchange splitting of exciton was employed for discussion. (C) 2003 American Institute of Physics.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

A 1Gb/s silicon photo-receiver in standard CMOS for 850-nm optical communication

A monolithic silicon CMOS optoelectronic integrated circuit (OEIC) was designed and fabricated with standard 0.6 mu m CMOS technology. This OEIC circuit consisted of an integrated double photodiode detector (DPD) and a preamplifier. The DPD detector exhibited high bandwidth by screening the bulk-generated diffusion carriers and suppressing the slow diffusion tail effect. The preamplifier exploited the regulated cascode (RGC) configuration as the input stage of receiver, thus isolating the influence of photodiode capacitance and input parasitic capacitance on bandwidth. Testing results showed that the bandwidth of OEIC was 700MHz, indicating the bit rate of 1Gb/s was achieved.

Hetero-epitaxial growth of ZnO films on silicon by low-pressure metal organic chemical vapor deposition

Quality ZnO films were successfully grown on Si(100) substrate by low-pressure metal organic chemical vapor deposition method in temperature range of 300-500 degrees C using DEZn and N2O as precursor and oxygen source respectively. The crystal structure, optical properties and surface morphology of ZnO films were characterized by X-ray diffraction, optical refection and atomic force microscopy technologies. It was demonstrated that the crystalline structure and surface morphology of ZnO films strongly depend on the growth temperature.

Blue Luminescent Properties of Silicon Nanowires Grown by a Solid-Liquid-Solid Method

Silicon nanowires (SiNWs) were grown directly from n-(111) single-crystal silicon (c-Si) substrate based on a solid-liquid-solid mechanism, and Au film was used as a metallic catalyst. The room temperature photoluminescence properties of SiNWs were observed by an Xe lamp with an exciting wavelength of 350 nm. The results show that the SiNWs exhibit a strongly blue luminescent band in the wavelength range 400-480 nm at an emission peak position of 420 nm. The luminescent mechanism of SiNWs indicates that the blue luminescence is attributed to the oxygen-related defects, which are in SiOx amorphous oxide shells around the crystalline core of SiNWs.

THE OXIDATION-KINETICS OF THIN POLYCRYSTALLINE SILICON FILMS

The oxidation dynamics and morphology of undoped and heavily phosphorus-doped polycrystalline silicon films oxidized at a wide temperature and time range in dry and wet O2 atmosphere have been investigated. It is shown that the oxidation rates of polycrystalline silicon films are different from that of single-crystal silicon when the oxidation temperature is below 1000-degrees-C. There is a characteristic oxidation time, t(c), under which the undoped polysilicon oxide is not only thicker than that of (100)-oriented single-crystal silicon, but also thicker than that of (111)-oriented single-crystal silicon. For phosphorus-doped polycrystalline silicon films, the oxide thickness is thinner not only than that of (111)-oriented, single-crystal silicon, but also thinner than that of (100)-oriented, single-crystal silicon. According to TEM cross-sectional studies, these characteristics are due to the enhanced oxidation at grain boundaries of polycrystalline silicon films. A stress-enhanced oxidation model has been proposed and used to explain successfully the enhanced oxidation at grain boundaries of polycrystalline silicon films. Using this model, the oxidation linear rate constant of polysilicon (B/A)poly has been calculated and used in the modeling of the oxidation dynamics. The model results are in good agreement with the experimental data over the entire temperature and time ranges studied.

A High-Performance Silicon Electro-Optic Phase Modulator with a Triple MOS Capacitor

We propose and analyze a novel Si-based electro-optic modulator with an improved metal-oxide-semiconductor (MOS) capacitor configuration integrated into silicon-on-insulator (SOI).Three gate-oxide layers embedded in the silicon waveguide constitute a triple MOS capacitor structure,which boosts the modulation efficiency compared with a single MOS capacitor.The simulation results demonstrate that the VπLπ product is 2.4V·cm.The rise time and fall time of the proposed device are calculated to be 80 and 40ps from the transient response curve,respectively,indicating a bandwidth of 8GHz.The phase shift efficiency and bandwidth can be enhanced by rib width scaling.

Dependence of ultra-thin gate oxide reliability on surface cleaning approach

In this paper, we investigate the effect of silicon surface cleaning prior to oxidation on the reliability of ultra-thin oxides. It is demonstrated that chemical preoxide grown in H2SO4/H2O2 (SPM) solution prior to oxidation provides better oxide integrity than both HF-based solution dipping and preoxide grown in RCA SC1 or SC2 solutions. It is also found that the oxides with SPM preoxide exhibit better hot-carrier immunity than the RCA cleaned oxides.

Nano-layer structure of silicon-on-insulator materials

Silicon-on-insulator (SOI) has been recognized as a promising semiconductor starting material for ICs where high speed and low power consumption are desirable, in addition to its unique applications in radiation-hardened circuits. In the present paper, three novel SOI nano-layer structures have been demonstrated. ULTRA-THIN SOI has been fabricated by separation by implantation of oxygen (SIMOX) technique at low oxygen ion energy of 45 keV and implantation dosage of 1.81017/cm2. The formed SOI layer is uniform with thickness of only 60 nm. This layer is of crystalline quality. and the interface between this layer and the buried oxide layer is very sharp, PATTERNED SOI nanostructure is illustrated by source and drain on insulator (DSOI) MOSFETs. The DSOI structure has been formed by selective oxygen ion implantation in SIMOX process. With the patterned SOI technology, the floating-body effect and self-heating effect, which occur in the conventional SOI devices, are significantly suppressed. In order to improve the total-dose irradiation hardness of SOI devices, SILICON ON INSULATING MULTILAYERS (SOIM) nano-structure is proposed. The buried insulating multilayers, which are composed of SiOx and SiNy layers, have been realized by implantation of nitride and oxygen ions into silicon in turn at different ion energies, followed by two steps of high temperature annealing process, respectively, Electric property investigation shows that the hardness to the total-dose irradiation of SOIM is remarkably superior to those of the conventional SIMOX SOI and the Bond-and-Etch-Back SOI.

Experimental Study on the Subthreshold Swing of Silicon Nanowire Transistors

SOI based wrap-gate silicon nanowire FETs are fabricated through electron beam lithography and wet etching. Dry thermal oxidation is used to further reduce the patterned fins cross section and transfer them into nanowires. Silicon nanowire FETs with different nanowire widths varying from 60 nm to 200 nm are fabricated and the number of the nanowires contained in a channel is also varied. The on-current (I-ON) and off-current (I-OFF) of the fabricated silicon nanowire FET are 0.59 mu A and 0.19 nA respectively. The subthreshold swing (SS) and the drain induced barrier lowering are 580 mV/dec and 149 mVN respectively due to the 30 nm thick gate oxide and 1015 cm(-3) lightly doped silicon nanowire channel. The nanowire width dependence of SS is shown and attributed to the fact that the side-gate parts of a wrap gate play a more effectual role as the nanowires in a channel get narrower. It seems the nanowire number in a channel has no effect on SS because the side-gate parts fill in the space between two adjacent nanowires.