Optimized design on high-power GaN-based Micro-LEDs - art. no. 684108

The structure of micro-LEDs was optimized designed. Optical, electrical and thermal characteristics of micro-LEDs were improved. The optimized design make micro-LEDs suitable for high-power device. The light extraction efficiency of micro-LEDs was analyzed by the means of ray tracing. The results shows that increasing the inclination angle of sidewall and height of mesa, and reducing the absorption of p and n electrode can enhance the light extraction efficiency of micro-LEDs. Furthermore, the total light output power can be boosted by increasing the density of micro-structures on the device. The high-power flip-chip micro-LEDs were fabricated, which has higher quantum efficiency than conventional BALED's. When the number of microstructure in micro-LEDs was increased by 57%, the light output power was enhanced 24%. Light output power is 82.88mW at the current of 350mA and saturation current is up to 800mA, all of these are better than BALED which was fabricated in the same epitaxial wafer. The IN characteristics of micro-LEDs are almost identical to BALED.

Design considerations for a silicon-based p-i-n phase modulator in a double ridge waveguide with side isolating grooves

We present detail design considerations and simulation results of a forward biased carrier injection p-i-n modulator integrated on SOI rib waveguides. To minimize the free carrier absorption loss while keeping the comparatively small lateral dimensions of the modulator as required for high speed operation, we proposed two structural improvements, namely the double ridge (terrace ridge) structure and the isolating grooves at both sides of the double ridge. With improved carrier injection and optical confinement structure, the simulated modulator response time is in sub-ns range and absorption loss is minimized.

Si based quantum cascade structure: from energy band structures design to materials growth

In this paper, we propose an n-type vertical transition bound-to-continuum Ge/SiGe quantum cascade structure utilizing electronic quantum wells in the L and Gamma valleys of the Ge layers. The optical transition levels are located in the quantum wells in the L valley. The Gamma-L intervalley scattering is used to depopulate the lower level and inject the electrons into the upper level. We also show that high quality Si1-yGey pseudosubstrate is obtained by thermal annealing of Si1-xGex/Ge/Si structure. (C) 2009 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

Design and Fabrication of a Photonic Crystal Channel Drop Filter Based on an Asymmetric Silicon-on-Insulator Slab

We report on the design and fabrication of a photonic crystal (PC) channel drop filter based on an asymmetric silicon-on-insulator (SOI) slab. The filter is composed of two symmetric stick-shape micro-cavities between two single-line-defect (W1) waveguides in a triangular lattice, and the phase matching condition for the filter to improve the drop efficiency is satisfied by modifying the positions and radii of the air holes around the micro-cavities. A sample is then fabricated by using electron beam lithography (EBL) and inductively coupled plasma (ICP) etching processes. The measured 0 factor of the filter is about 1140, and the drop efficiency is estimated to be 73% +/- 5% by fitting the transmission spectrum.

On the design and simulation of high speed electro-optic modulator based on SOI waveguide MOS dual capacitor structure

zhangdi于2010-03-29批量导入

Design and Fabrication of Low-microwave loss Coplannar Waveguide and precise V groove on Silicon Substrate for Optoelectronic Packaging - art. no. 601938

Optoelectronic packaging has become a most important factor that influences the final performance and cost of the module. In this paper, low microwave loss coplanar waveguide(CPW) on high resistivity silicon(HRS) and precise V groove in silicon substrate were successfully fabricated. The microwave attenuation of the CPW made on HRS with the simple process is lower than 2 dB/cm in the frequency range of 0 similar to 26GHz, and V groove has the accuracy in micro level and smooth surface. These two techniques built a good foundation for high frequency packaging and passive coupling of the optoelectronic devices. Based on these two techniques, a simple high resistivity silicon substrate that integrated V groove and CPW for flip-chip packaging of lasers was completed. It set a good example for more complicate optoelectronic packaging.

VCSEL-based parallel optical transmission module

This paper describes the design process and performance of the optimized parallel optical transmission module. Based on 1x12 VCSEL (Vertical Cavity Surface Emitting Laser) array, we designed and fabricated the high speed parallel optical modules. Our parallel optical module contains a 1x12 VCSEL array, a 12 channel CMOS laser driver circuit, a high speed PCB (Printed Circuit Board), a MT fiber connector and a packaging housing. The L-I-V characteristics of the 850nm VCSEL was measured at the operating current 8mA, 3dB frequency bandwidth more than 3GHz and the optical output 1mW. The transmission rate of all 12 channels is 30Gbit/s, with a single channel 2.5Gbit/s. By adopting the integration of the 1x12 VCSEL array and the driver array, we make a high speed PCB (Printed Circuit Board) to provide the optoelectronic chip with the operating voltage and high speed signals current. The LVDS (Low-Voltage Differential Signals) was set as the input signal to achieve better high frequency performance. The active coupling was adopted with a MT connector (8 degrees slant fiber array). We used the Small Form Factor Pluggable (SFP) packaging. With the edge connector, the module could be inserted into the system dispense with bonding process.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

SBS-based slow light in optical fibers: optimum design considerations for undistorted slow-light signal propagation in steady-state and transient regimes

SPIE

Design for an IO block array in a tile-based FPGA

A design for an IO block array in a tile-based FPGA is presented.Corresponding with the characteristics of the FPGA, each IO cell is composed of a signal path, local routing pool and configurable input/output buffers.Shared programmable registers in the signal path can be configured for the function of JTAG, without specific boundary scan registers/latches, saving layout area.The local routing pool increases the flexibility of routing and the routability of the whole FPGA.An auxiliary power supply is adopted to increase the performance of the IO buffers at different configured IO standards.The organization of the IO block array is described in an architecture description file, from which the array layout can be accomplished through use of an automated layout assembly tool.This design strategy facilitates the design of FPGAs with different capacities or architectures in an FPGA family series.The bond-out schemes of the same FPGA chip in different packages are also considered.The layout is based on SMIC 0.13μm logic 1P8M salicide 1.2/2.5 V CMOS technology.Our performance is comparable with commercial SRAM-based FPGAs which use a similar process.

Design of a Frequency Divider with Reduced Complexity Based on a Resonant Tunneling Diode

A novel edge-triggered D-flip-flop based on a resonant tunneling diode (RTD) is proposed and used to construct a binary frequency divider. The design is discussed in detail and the performance of the circuit is verified using SPICE. Relying on the nonlinear characteristics of RTD, we reduced the number of components used in our DFF circuit to only half of that required using conventional CMOS SCFL technology.

Design of spectrometer based on volume phase grating for near infrared range

In order to design and fabricate a spectrometer for the infrared range widely used in the different applications, Volume Phase Grating (VPG) with. low Polarization Dependence Loss (PDL) and high efficiency has been adopted as the dispersion element. VPG is constructed by coating an optical substrate with a thin film of dichromated. gelatin and exposing the film to two mutually coherent laser beams to form index modulation. The diffraction efficiency for a VPG is governed by Bragg effects. The depth (d) and index modulation contrast of the grating structure control the efficiency at which the light is diffracted when the Bragg condition is satisfied. Gradient index lens with high performance and low aberration are used as collimating system instead of standard lens. The spot diagrams and MTF curve of the collimating lens are shown in the paper. The receive system is InCaAs photodiode (PD) array including 512 pixels with 25 mum pitch. The spectrum resolution of the spectrometer reaches to 0.2nm and wavelength accuracy is 40pm.