78 resultados para linearity


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This study develops a fiber Bragg grating (FBG) pressure sensor partly shielded with a metal tube. The thermal-strain cross effect is avoided and its pressure sensitivity is increased to -2.44 x 10(-3) MPa, about 1200 times as that of a bare fiber grating. Due to its good sensing linearity, this sensor can be applied in the measurement of hydraulic pressure and vibration. (c) 2006 Elsevier Inc. All rights reserved.

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This paper presents a 2GS/s 10-bit CMOS digital-to-analog converter (DAC). This DAC consists of a unit current-cell matrix for 6MSBs and another unit current-cell matrix for 4LSBs, trading off between the precision and size of the chip. The Current Mode Logic (CML) is used to ensure high speed, and a double Centro-symmetric current matrix is designed by the Q(2) random walk strategy in order to ensure the linearity of the DAC. The DAC occupies 2.2 x 2.2 mm2 of die area, and consumes 790mw at a single 3.3V power supply.

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In this paper, a wide-band low noise amplifier, two mixers and a VCO with its buffers implemented in 50GHz 0.35 mu m SiGe BiCMOS technology for dual-conversion digital TV tuner front-end is presented. The LNA and up-converting mixer utilizes current injection technology to achieve high linearity. Without using inductors, the LNA achieves 0.1-1GHz wide bandwidth and 18.8-dB gain with less than 1.4-dB gain variation. The noise figure of the LNA is less than 5dB and its 1dB compression point is -2 dBm. The IIP3 of two mixers is 25-dBm. The measurement results show that the VCO has -127.27-dBc/Hz phase noise at 1-MHz offset and a linear gain of 32.4-MHz/V between 990-MHz and 1.14-GHz. The whole chip consume 253mW power with 5-V supply.

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This paper describes a 12-bit 300 MHz CMOS DAC for high-speed system applications. The proposed DAC consists of a unit current-cell matrix for 8 MSBs and a binary-weighted array for 4 LSBs. In order to ensure the linearity of DAC, a double Centro symmetric current matrix is designed by using the Q(2) random walk strategy. To minimize the feedthrough and improve the dynamic performance, the drain of the switching transistors is isolated from the output lines by adding two cascoded transistors.

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We present a model for electrons confined in narrow conducting channels by a parabolic well under moderate to high magnetic fields which takes into account a cutoff in the filling of the subbands. Such a cutoff gives rise to energy-separated subbands and a two-dimensional (2D) like subband depopulation, resulting in a relation between sublevel index n and inverse magnetic field B-1 such that in the high-field regime it changes over to the well-known 2D form as expected, and in the moderate field regime it shows pronounced deviation from linearity. This agrees well with the experimental results. The linear region of the n-B-1 experimental plot is believed to arise from the two dimensionality of the system. Calculations show that no resolvable 1D sublevel exists in the 0.5-mu-m-wide wire at very small magnetic fields (including zero field), which agrees qualitatively with the experimental results found in other wires that the Hall resistance, R(H), approaches its classical value B/n(e)e in this region and R(H) = 0 at B = 0, where n(e) is the electron concentration. In this model the linear and nonlinear regions in the experimental n-B-1 plot are used to extract the characteristic frequency omega-0, and the effective 2D electron concentration N(e)2D, respectively.

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An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

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We present the design of a wide-band low-noise amplifier (LNA) implemented in 0.35μm SiGe BiCMOS technology for cable and terrestrial tuner applications. The LNA utilizes current injection to achieve high linearity. Without using inductors, the LNA achieves 0.1 ~ 1GHz wide bandwidth and 18. 8dB gain with less than 1.4dB of gain variation. The noise figure of the wideband LNA is 5dB, and its 1dB compression point is - 2dBm and IIP3 is 8dBm. The LNA dissipates 120mW of power with a 5V supply.

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The proposed DAC consists of a unit current-cell matrix for 8MSBs and a binary-weighted array for 4LSBs, trading-off between the precision, speed, and size of the chip. In order to ensure the linearity of the DAC, a double Centro symmetric current matrix is designed by the Q2 random walk strategy. To achieve better dynamic performance, a latch is added in front of the current switch to change the input signal, such as its optimal cross-point and voltage level. For a 12bit resolution,the converter reaches an update rate of 300MHz.

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A novel ameliorated phase generated carrier (PGC) demodulation algorithm based on arctangent function and differential-self-multiplying (DSM) is proposed in this paper. The harmonic distortion due to nonlinearity and the stability with light intensity disturbance (LID) are investigated both theoretically and experimentally. The nonlinearity of the PGC demodulation algorithm has been analyzed and an analytical expression of the total-harmonic-distortion (THD) has been derived. Experimental results have confirmed the low harmonic distortion of the ameliorated PGC algorithm as expected by the theoretical analysis. Compared with the traditional PGC-arctan and PGC-DCM algorithm, the ameliorated PGC algorithm has a much lower THD as well as a better signal-to-noise-and-distortion (SINAD). A THD of below 0.1% and a SINAD of 60 dB have been achieved with PGC modulation depth (value) ranges from 1.5 to 3.5 rad. The stability performance with LID has also been studied. The ameliorated PGC algorithm has a much higher stability than the PGC-DCM algorithm. It can keep stable operations with LID depth as large as 26.5 dB and LID frequency as high as 1 kHz. The system employing the ameliorated PGC demodulation algorithm has a minimum detectable phase shift of 5 mu rad/root Hz @ 1 kHz, a large dynamic range of 120 dB @ 100 Hz, and a high linearity of better than 99.99%.

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Fiber Bragg grating (FBG) sensor for monitoring the electromagnetic strain in a low temperature superconducting (LTS) magnet was studied. Before used to LTS magnet strain sensing, the strain response of the sensor with 1.54-mu m wavelength at liquid helium was experimentally studied. It was found that the wavelength shift showed good linearity with longitudinal applied loads and the strain sensitivity is constant at 4.2 K. And then, the hoop strain measurement of a LTS magnet was carried out on the basis of measured results. Furthermore, the finite element method (FEM) was used to simulate the magnet strain. The difference between the experimental and numerical analysis results is very small.

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Fiber Bragg grating (FBG) sensor for monitoring the electromagnetic strain in a low temperature superconducting (LTS) magnet was studied. Before used to LTS magnet strain sensing, the strain response of the sensor with 1.54-mu m wavelength at liquid helium was experimentally studied. It was found that the wavelength shift showed good linearity with longitudinal applied loads and the strain sensitivity is constant at 4.2 K. And then, the hoop strain measurement of a LTS magnet was carried out on the basis of measured results. Furthermore, the finite element method (FEM) was used to simulate the magnet strain. The difference between the experimental and numerical analysis results is very small.

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In this paper, we describe the structure and readout system of a two-dimension positional sensitive CsI(Tl) detector, and investigates the relation between energy lose and light output of the CsI(Tl) detector with secondary beams in intermediate energy.Bρ+(ΔE-TOF) method was used to distinguish the secondary beam.Linearity of the position signals of the CsI(Tl) was corrected.Energy signals from the CsI(Tl) detector were calibrated using the relationship of the Z, A and the light output response of the incid...中文摘要:描述了一种双维位置灵敏CsI(Tl)探测器的结构及其读出系统,用中能次级束研究其能损与光输出关系。使用Bρ+(ΔE-TOF)方法鉴别次级束,刻度了CsI(Tl)探测器位置信号的线性,并用其光输出与入射粒子的A、Z关系刻度其能量。结果表明,CsI(Tl)探测器输出信号的ADC读出与QDC读出(即其光输出)有很好的线性关系。

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The clinical trials of tumor therapy using heavy ions beam C-12 are now in progress at Institute of Modem Physics in Lanzhou. In order to achieve the precise radiotherapy with the high energy C-12 beam in active pencil beam scanning mode, we have developed an ionization chamber(IC) as an online monitor for beam intensity and also a dosimeter after calibration. Through the choosing of working gas and voltage, optimizing of the electrics and the read-out system, calibrating the linearity, the detector system provide us one of the simple and highly reliable way to monitoring the beam during the active pencil beam scanning treatments. The measurement results of this detector system show that it could work well under the condition of high energy C-12 beam in active pencil beam scanning mode.

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In this paper, to design a new preamplifier for optimum performances with charged-particle or heavy-ion detectors, the CMOS FET is implemented as a feedback capacitor C-fp, so that the entire system should be built only with MOSFET. This work is a revolution design because to realize an ASIC for a preamplifier circuit, the capacitor will also be included. We succeed after a simulation to maintain a rise time less than 3 ns, the output resistance less than 94 Omega and the linearity almost good.

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In this paper, the design and analysis of a new low noise charge sensitive preamplifier for silicon strip, Si(Li), CdZnTe and CsI detectors etc. with switch control feedback resistance were described, the entire system to be built using the CMOS transistors. The circuit configuration of the CSP proposed in this paper can be adopted to develop CMOS-based Application Specific Integrated Circuit further for Front End Electronics of read-out system of nuclear physics, particle physics and astrophysics research, etc. This work is an implemented design that we succeed after a simulation to obtain a rise time less than 3ns, the output resistance less than 94 Omega and the linearity almost good.