A Compact Direct Digital Frequency Synthesizer for System-on-chip

A compact direct digital frequency synthesizer (DDFS) for system-on-chip (SoC) is developed in this paper. For smaller chip size and lower power consumption, the phase to sine mapping data is compressed by using sine symmetry technique, sine-phase difference technique, quad line approximation (QLA) technique and quantization and error read only memory (QE-ROM) technique. The ROM size is reduced by 98 % using the techniques mentioned above. A compact DDFS chip with 32-bit phase storage depth and a 10-bit on-chip digital to analog converter(DAC) has been successfully implemented using standard 0.35um CMOS process. The core area of the DDFS is 1.6mm(2). It consumes 167 mW at 3.3V, and its spurious free dynamic range (SFDR) is 61dB.

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

The Deposition and Burning Characteristics During Slagging Co-Firing Coal and Wood: Modeling and Numerical Simulation

Numerical analysis was used to study the deposition and burning characteristics of combining co-combustion with slagging combustion technologies in this paper. The pyrolysis and burning kinetic models of different fuels were implanted into the WBSF-PCC2 (wall burning and slag flow in pulverized co-combustion) computation code, and then the slagging and co-combustion characteristicsespecially the wall burning mechanism of different solid fuels and their effects on the whole burning behavior in the cylindrical combustor at different mixing ratios under the condition of keeping the heat input samewere simulated numerically. The results showed that adding wood powder at 25% mass fraction can increase the temperature at the initial stage of combustion, which is helpful to utilize the front space of the combustor. Adding wood powder at a 25% mass fraction can increase the reaction rate at the initial combustion stage; also, the coal ignitability is improved, and the burnout efficiency is enhanced by about 5% of suspension and deposition particles, which is helpful for coal particles to burn entirely and for combustion devices to minimize their dimensions or sizes. The results also showed that adding wood powder at a proper ratio is helpful to keep the combustion stability, not only because of the enhancement for the burning characteristics, but also because the running slag layer structure can be changed more continuously, which is very important for avoiding the abnormal slag accumulation in the slagging combustor. The theoretic analysis in this paper proves that unification of co-combustion and slagging combustion technologies is feasible, though more comprehensive and rigorous research is needed.

Uniform mems chip temperatures in the nucleate boiling heat transfer region by selecting suitable, medium boiling number range

The not only lower but also uniform MEMS chip temperatures can he reached by selecting suitable boiling number range that ensures the nucleate boiling heat transfer. In this article, boiling heat transfer experiments in 10 silicon triangular microchannels with the hydraulic diameter of 55.4 mu m were performed using acetone as the working fluid, having the inlet liquid temperatures of 24-40 degrees C, mass fluxes of 96-360 kg/m(2)s, heat fluxes of 140-420 kW/m(2), and exit vapor mass qualities of 0.28-0.70. The above data range correspond to the boiling number from 1.574 x 10(-3) to 3.219 x 10(-3) and ensure the perfect nucleate boiling heat transfer region, providing a very uniform chip temperature distribution in both streamline and transverse directions. The boiling heat transfer coefficients determined by the infrared radiator image system were found to he dependent on the heat Axes only, not dependent on the mass Axes and the vapor mass qualities covering the above data range. The high-speed flow visualization shows that the periodic flow patterns take place inside the microchannel in the time scale of milliseconds, consisting of liquid refilling stage, bubble nucleation, growth and coalescence stage, and transient liquid film evaporation stage in a full cycle. The paired or triplet bubble nucleation sites can occur in the microchannel corners anywhere along the flow direction, accounting for the nucleate boiling heat transfer mode. The periodic boiling process is similar to a series of bubble nucleation, growth, and departure followed by the liquid refilling in a single cavity for the pool boiling situation. The chip temperature difference across the whole two-phase area is found to he small in a couple of degrees, providing a better thermal management scheme for the high heat flux electronic components. Chen's [11 widely accepted correlation for macrochannels and Bao et al.'s [21 correlation obtained in a copper capillary tube with the inside diameter of 1.95 mm using R11 and HCFC123 as working fluids can predict the present experimental data with accepted accuracy. Other correlations fail to predict the correct heat transfer coefficient trends. New heat transfer correlations are also recommended.

On-Chip All-Optical Passive 3.55 Gbit/s NRZ-to-PRZ Format Conversion Using a High-Q Silicon-Based Microring Resonator

We report the experimental result of all-optical passive 3.55 Gbit/s non-return-to-zero (NRZ) to pseudo-return-to-zero (PRZ) format conversion using a high-quality-factor (Q-factor) silicon-based microring resonator notch filter on chip. The silicon-based microring resonator has 23800 Q-factor and 22 dB extinction ratio (ER), and the PRZ signals has about 108 ps width and 4.98 dB ER.

An asymmetric MOSFET-C band-pass filter with on-chip charge pump auto-tuning

An asymmetric MOSFET-C band-pass filter(BPF)with on chip charge pump auto-tuning is presented.It is implemented in UMC (United Manufacturing Corporation)0.18μm CMOS process technology. The filter system with auto-tuning uses a master-slave technique for continuous tuning in which the charge pump OUtputs 2.663 V, much higher than the power supply voltage, to improve the linearity of the filter. The main filter with third order low-pass and second order high-pass properties is an asymmetric band-pass filter with bandwidth of 2.730-5.340 MHz. The in-band third order harmonic input intercept point(HP3) is 16.621 dBm,wim 50 Ω as the source impedance. The input referred noise iS about 47.455μVrms. The main filter dissipates 3.528 mW while the auto-tuning system dissipates 2.412 mW from a 1.8 V power supply. The filter with the auto-tuning system occupies 0.592 mm~2 and it can be utilized in GPS (global positioning system)and Bluetooth systems.

Modified Holographic Exposure to Fabricate Varied Bragg Grating in an Identical Chip

A new fabricating method is demonstrated to realize two different Bragg gratings in an identical chip using traditional holographic exposure. Polyimide is used to protect one Bragg grating during the first period. The technical process of this method is as simple as that of standard holographic exposure

Multiple Quantum Well SEED Arrays for Flip-Chip Bonding Optoelectronic Smart Pixels

于2010-11-23批量导入

Optoelectronic Smart Pixels Comprising Flip-Chip-Bonded GaAs/AlGaAs MQW Detectors and Modulators on Silicon CMOS Circuit

于2010-11-23批量导入

16-channel VCSEL based multiple chip modules

　

VCSEL based optoelectronic multiple chip modules

We report on optoelectronic multiple chip modules, consisting of vertical cavity surface emitting laser(VCSEL), photodetector and 1.2 mum CMOS electronic circuit, The hybrid integrated components operate at a date rate of 155Mb/s, which could be used in optical interconnects for multiple computers.

Flip-chip bonded hybrid CMOS/SEED optoelectronic smart pixels

Hybrid integration of GaAs/AlGaAs multiple quantum well self electro-optic effect device (SEED) arrays are demonstrated flip-chip bonded directly onto 1 mu m silicon CMOS circuits. The GaAs/AlGaAs MQW devices are designed for 850 nm operation. Some devices are used as input light detectors and others serve as output light modulators. The measurement results under applied biases show good optoelectronic characteristics of elements in SEED arrays. Nearly the same reflection spectrum is obtained for the different devices at an array and the contrast ratio is more than 1.2:1 after flip-chip bonding and packaging. The transimpedance receiver-transmitter circuit can be operated at a frequency of 300 MHz.

Injection by hydrostatic pressure in conjunction with electrokinetic force on a microfluidic chip

A simple method was developed for injecting a sample on a cross-form microfluidic chip by means of hydrostatic pressure combined with electrokinetic forces. The hydrostatic pressure was generated simply by adjusting the liquid level in different reservoirs without any additional driven equipment such as a pump. Two dispensing strategies using a floating injection and a gated injection, coupled with hydrostatic pressure loading, were tested. The fluorescence observation verified the feasibility of hydrostatic pressure loading in the separation of a mixture of fluorescein sodium salt and fluorescein isothiocyanate. This method was proved to be effective in leading cells to a separation channel for single cell analysis.