When is `partial' adequate? A logic-based proof technique using partial specifications

A technique is presented for ascertaining when a (finite-state) partial process specification is adequate, in the sense of being specified enough, for contexts in which it is to be used. The method relies on the automatic generation of a modal formula from the partial specification; if the remainder of the network satisfies this formula, then any process that meets the specification is guaranteed to ensure correct behavior of the overall system. Using the results, the authors develop compositional proof rules for establishing the correctness of networks of parallel processes and illustrate their use with several examples

A voltage-controlled ring oscillator using InP full enhancement-mode HEMT logic

A voltage-controlled ring oscillator (VCO) based on a full enhancement-mode InAIAs/InGaAs/InP high electron mobility transistor (HEMT) logic is proposed. An enhancement-mode HEMT (E-HEMT) is fabricated, whose threshold is demonstrated to be 10 mV. The model of the E-HEMT is established and used in the SPICE simulation of the VCO. The result proves that the full E-HEMT logic technology can be applied to the VCO. And compared with the HEMT DCFL technology, the complexity of our fabrication process is reduced and the reliability is improved.

A Monolithic Integrated Logic Circuit of Resonant Tunneling Diodes and a HEMT

A technology for the monolithic integration of resonant tunneling diodes (RTDs) and high electron mobility transistors (HEMTs) is developed. Molecular beam epitaxy is used to grow an RTD on a HEMT structure on GaAs substrate. The RTD has a room temperature peak-to-valley ratio of 5.2:1 with a peak current density of 22.5kA/cm~2. The HEMT has a 1μm gate length with a-1V threshold voltage. A logic circuit called a monostableto-bistable transition logic element (MOBILE) circuit is developed. The experimental result confirms that the fabricated logic circuit operates successfully with frequency operations of up to 2GHz.

16×0．8nm Si基SiO2阵列波导光栅设计、制备及测试

叙述了一个完整的16通道硅基二氧化硅阵列波导光栅(AWG)的设计、制备及测试过程。通道间隔为0．8nm(100GHz)，解复用器的插入损耗为16．8dB，其中材料损耗为11．95dB，相邻通道串扰小于一17dB，通道插损非均匀性小于2．2dB。

Design,Fabrication,and Testing of Single-Side Alignment of 16×0.8nm Arrayed-Waveguide Grating

A novel design of 100GHz-spaced 16channel arrayed-waveguide grating (AWG) based on silica-on-silicon chip is reported.AWG is achieved by adding a Y-branch to the AWG and arranging the input/output channel in a neat row,so the whole configuration can be aligned and packaged using only one fiber-array.This configuration can decrease the device's size,enlarge the minimum radius of curvature,save time on polishing and alignment,and reduce the chip's fabrication cost.

16×0.8nm硅基二氧化硅阵列波导光栅设计

给出了更为合理的阵列波导光栅(AWG)的设计原则.在设计时兼顾了输出谱的非均匀性Lu和输出通道数N的要求,克服了设计中可能引起通道数N丢失和不考虑输出谱非均匀性Lu的缺点.用该方法设计了折射率差为0.75%和16×0.8nm的硅基二氧化硅AWG.采用广角有限差分束传播方法(FD-BPM)对所设计的AWG进行了输出谱的模拟,得到了插损为-1.5dB、串扰为-48dB、通道非均匀性约为1dB的AWG,设计指标达到了商用要求。

16×0.8nm硅基二氧化硅AWG性能优化

对设计的折射率差为0.75%的16×0.8 nm硅基二氧化硅阵列波导光栅(AWG),围绕插损和串扰问题,采用广角有限差分束传播方法(FD-BPM)进行了数值模拟和优化.通过优化在输入波导、阵列波导的喇叭口,得到了插损为1.5 dB、串扰为-48 dB的AWG,优化后的指标已达到商用要求.