The effect of Fabry-Perot interference on the packaging of SOI-based optoelectronic devices

During the packaging of optoelectrome device, a problem always met is the instability of output power. The main effect causing this problem, Fabry-Perot interference, is discussed in this paper. Both theoretical analysis and experimental test are carried out and in good agreement. As an example of avoiding the disadvantage of Fabry-Perot interference, the packaging process of Silicon-on-Insulator (SOI) based Variable Optical Attenuator(VOA) is shown at last.

Improved diphasic nc-si/a-si : H I-layer materials using PECVD

Two series of films has been prepared by using a new regime of plasma enhanced chemical vapor deposition (PECVD) in the region adjacent to the phase transition from amorphous to crystalline state. The photoelectronic properties of the films have been investigated as a function of crystalline fraction. In comparison with typical a-Si:H, these diphasic films with a crystalline fraction less than 0.3 show a similar optical absorption coefficient, higher mobility life-time product ( LT) and higher stability upon light soaking. By using the diphasic nc-Si/a-Si films as the intrinsic layer, a p-i-n junction solar cell has been prepared with an initial efficiency of 9. 10 % and a stabilized efficiency of 8.56 % (AM 1.5, 100 mW/cm(2)).

Homoepitaxial growth and MOS structures of 4H-SiC on off oriented n-type (0001)Si-faces

Homoepitaxial growth of 4H-SiC on off-oriented n-type Si-face (0001) substrates was performed in a home-made hot-wall low pressure chemical vapor deposition (LPCVD) reactor with SiH4 and C2H4 at temperature of 1500 C and pressure of 20 Torr. The surface morphology and intentional in-situ NH3 doping in 4H-SiC epilayers were investigated by using atomic force microscopy (AFM) and secondary ion mass spectroscopy (SIMS). Thermal oxidization of 4H-SiC homoepitaxial layers was conducted in a dry O-2 and H-2 atmosphere at temperature of 1150 C. The oxide was investigated by employing x-ray photoelectron spectroscopy (XPS). 4H-SiC MOS structures were obtained and their C-V characteristics were presented.

Hetero-epitaxial growth of ZnO films on silicon by low-pressure metal organic chemical vapor deposition

Quality ZnO films were successfully grown on Si(100) substrate by low-pressure metal organic chemical vapor deposition method in temperature range of 300-500 degrees C using DEZn and N2O as precursor and oxygen source respectively. The crystal structure, optical properties and surface morphology of ZnO films were characterized by X-ray diffraction, optical refection and atomic force microscopy technologies. It was demonstrated that the crystalline structure and surface morphology of ZnO films strongly depend on the growth temperature.

Subretinal implantable artificial photoreceptor

The present study reports a subretinal implant device which can imitate the function of photoreceptor cells. Photodiode (PD) arrays on the chip translate the incident light into current according to the intensity of light. With an electrode at the end of every photodiode, the PDs transfer the current to the remnant healthy visual cells such as bipolar cells and horizontal cells and then activate these cells. Biocompatible character of the materials and artificial photoreceptor itself were tested and the photoelectric characteristics of the chips in simulative condition were described and discussed.

Circuit design and simulation of a CMOS-based preamplifier for brain neural signals

A novel CMOS-based preamplifier for amplifying brain neural signal obtained by scalp electrodes in brain-computer interface (BCI) is presented in this paper. By means of constructing effective equivalent input circuit structure of the preamplifier, two capacitors of 5 pF are included to realize the DC suppression compared to conventional preamplifiers. Then this preamplifier is designed and simulated using the standard 0.6 mu m MOS process technology model parameters with a supply voltage of 5 volts. With differential input structures adopted, simulation results of the preamplifier show that the input impedance amounts to more than 2 Gohm with brain neural signal frequency of 0.5 Hz-100 Hz. The equivalent input noise voltage is 18 nV/Hz(1/2). The common mode rejection ratio (CMRR) of 112 dB and the open-loop differential gain of 90 dB are achieved.

Improvement of the electrical property of semi-insulating InP by suppression of compensation defects

Semi-insulating (SI) InP obtained by iron phosphide ambient annealing has very low concentration of deep level defects and better electrical property than SI-InP annealed in phosphorus ambient. The defect suppression phenomenon correlates with Fe diffusion and substitution in the annealing process. Analysis of the experimental result suggests that a high activation ratio of incorporated Fe in InP has an effect of defect suppression in Fe-doped and Fe-diffused SI-InP.

A novel low-power input-independent MOS AC/DC charge pump

This paper presents a novel fully integrated MOS AC to DC charge pump with low power dissipation and stable output for RFID applications. To improve the input sensitivity, we replaced Schottky-diodes in conventional charge pumps with MOS diodes with zero threshold, which has less process defects and is thus more compatible with other circuits. The charge pump in a RFID transponder is implemented in a 0.35um CMOS technology with 0.24 sq mm die size. The analytical model of the charge pump and the simulation results are presented.

An Accurate and Fast Behavioral Model for PLL Frequency Synthesizer Phase Noise/Spurs Prediction

This paper presents a behavior model for PLL Frequency Synthesizer. All the noise sources are modeled with noise voltages or currents in time-domain. An accurate VCO noise model is introduced, including both thermal noise and 1/f noise. The behavioral model can be co-simulated with transistor level circuits with fast speed and provides more accurate phase noise and spurs prediction. Comparison shows that simulation results match very well with measurement results.

An Ultra Low Power Non-volatile Memory in Standard CMOS Process for Passive RFID Tags

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 mu M standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780KHz, the current consumption of the memory is 1.8 mu A (3.6 mu A) at the read (write) rate of 1.3Mb/s (0.8Kb/s).

A Novel Architecture of Vision Chip for Fast Traffic Lane Detection and FPGA Implementation

This paper presents a novel architecture of vision chip for fast traffic lane detection (FTLD). The architecture consists of a 32*32 SIMD processing element (PE) array processor and a dual-core RISC processor. The PE array processor performs low-level pixel-parallel image processing at high speed and outputs image features for high-level image processing without I/O bottleneck. The dual-core processor carries out high-level image processing. A parallel fast lane detection algorithm for this architecture is developed. The FPGA system with a CMOS image sensor is used to implement the architecture. Experiment results show that the system can perform the fast traffic lane detection at 50fps rate. It is much faster than previous works and has good robustness that can operate in various intensity of light. The novel architecture of vision chip is able to meet the demand of real-time lane departure warning system.

A Novel 0.72-6.2GHz Continuously-Tunable Delta Sigma Fractional-N Frequency Synthesizer

This paper presents a wideband Delta Sigma-based fractional-N synthesizer with three integrated quadrature VCOs for multiple-input multiple-output (MIMO) wireless communication applications. It continuously covers a wide range frequency from 0.72GHz to 6.2GHz that is suitable for multiple communication standards. The synthesizer is designed in 0.13-um RE CMOS process. The dual clock full differential multi-modulus divide (MMD) with low power consumption can operate over 9GHz under the worst condition. In the whole range frequency from 0.72GHz to 6.2GHz, the maximal tuning range of the QVCOs reaches 33.09% and their phase noise is -119d8/Hz similar to 124d8/Hz @1MHz. Its current is less than 12mA at a 1.2V voltage supply when it operates at the highest frequency of 6.2GHz.

A Simplified Soft-output QRD-M MIMO Detector

In this paper, a low-complexity soft-output QRD-M detection algorithm is proposed for high-throughput Multiple-input multiple-output (MIMO) systems. By employing novel expansion on demand and distributed sorting scheme, the proposed algorithm can reduce 70% and 85% foundational operations for 16-QAM and 64-QAM respectively compared to the conventional QRD-M algorithm. Furthermore, the proposed algorithm can yield soft information to improve the bit error rate (BER) performance. Simulation results show that the proposed algorithm can achieve a near-NIL detection performance with less foundational operations

Simulation on Gain Recovery of Quantum Dot Semiconductor Optical Amplifiers by Rate Equation

The gain recoveries in quantum dot semiconductor optical amplifiers are numerically studied by rate equation models. Similar to the optical pump-probe experiment, the injection of double optical pulses is used to simulate the gain recovery of a weak continuous signal for the QD SOAs. The gain recoveries are fitted by a response function with multiple exponential terms. For the pulses duration of 10 ps, the gain recovery can be described by three exponential terms with the time constants, and for the pulse with the width of 150 fs, the gain recovery can be described by two exponential terms, the reason is that the short pulse does not consume lot of carriers.

Calculation of Light Delay by FDTD Technique and Pade Approximation

The time delay for light transmission in a coupled microring waveguide structure is calculated from the phase shift of the transmission coefficient obtained by Pade approximation with Baker's algorithm from FDTD Output. The results show that the Pade approximation is a powerful tool for saving time in FDTD simulation.