Observation of N-Shaped Negative Differential Resistance in GaAs-Based Modulation-Doped Field Effect Transistor with InAs Quantum Dots

N-shaped negative differential resistance (NDR) with a high peak-to-valley ratio (PVR) is observed in a GaAs-based modulation-doped field effect transistor (MODFET) with InAs quantum dots (QDs) in the barrier layer (QDFET) compared with a GaAs MODFET. The NDR is explained as the real-space transfer (RST) of high-mobility electrons in a channel into nearby barrier layers with low mobility, and the PVR is enhanced dramatically upon inserting the QD layer. It is also revealed that the QD layer traps holes and acts as a positively charged nano-floating gate after a brief optical illumination, while it acts as a negatively charged nano-floating gate and depletes the adjacent channel when charged by the electrons. The NDR suggests a promising application in memory or high-speed logic devices for the QDFET structure.

一种红外探测器专用77K工作CMOS前置放大器

利用single endedfolded cascode结构和MOS管工作在线性区做反馈电阻,实现了一种在77K工作的高性能低功耗、低噪声前置放大器.分析了它的噪声特性,提出了减少噪声的措施.此前置放大器用1.2μm的标准CMOS工艺制造完成.经过测试,这种前置放大器在低温77K下能正常工作,反馈电阻大小为兆欧级,线性度达到了1%,等效输入噪声电流仅0.03pA/Hz,功耗小于1mW.

用于粒子探测器的CMOS FET采样保持电路的设计与仿真(英文)；Design and Simulation of Track/Hold Circuit with CMOS FET for Particle Detector

介绍了一个峰保持电路。该电路适用于silicon strip,Si(Li),CdZn Te and CsI等探测器,实现采样-保持功能。已成功进行了基于CMOSFET的采样-保持电路的设计和仿真,通过使用Proteus的PSPICE仿真器和BSIMV3.3模型参数完成了电路性能的仿真。同时,实现了采样时间可在60ns到4.44s范围内进行选择,该电路具有较好的线性。

基于CMOS器件的专用放大电路设计

随着国家大科学工程兰州重离子加速器冷却储存环(HIRFL-CSR)建成，CSRm实验探测系统也正在建设当中。CSRm实验探测系统具有多种探测器数万个探测单元。对于这样先进的探测器和大型实验探测系统采用传统的电子学仪器和方法已经无法构成读出电子学系统和数据获取系统，对前端读出电子学系统、数据获取系统提出更高的要求。因此，采用专用集成电路芯片(ASIC)构成前端读出电子学系统是最可行的方法。本论文所述的基于MOS管的专用放大电路设计正是基于集成电路（ASIC）芯片构建前端读出电子学系统的前期研究子部分。作为ASIC前端读出电子学研究的一部分，本论文主要阐述基于MOS器件的放大电路的研究，主要包括以下内容： 1、设计及实现基于CMOS管的电荷灵敏前置放大器，最后给出制作PCB板后的实验室调试结果； 2、设计仿真基于DMOS管的电荷灵敏前置放大器，对仿真结果进行讨论； 3、利用集成电路设计软件Tanner Pro实现电荷灵敏前置放大器的物理版图设计

Hybrid metal-base transistor with base of sulfonated polyaniline and fullerene emitter

We demonstrate hybrid vertical architecture transistors that operate like metal-base transistors, using n-type silicon as the collector, sulfonated polyaniline as the base, and C-60 fullerene as the emitter. Electrical measurements suggest that the sulfonated polyaniline base effectively screens the emitter from electric field variations occurring in the collector leading to the metal-base transistor behavior.

Hybrid permeable metal-base transistor with large common-emitter current gain and low operational voltage

We demonstrate the suitability of N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB), an organic semiconductor widely used in organic light-emitting diodes (OLEDs), for high-gain, low operational voltage nanostructured vertical-architecture transistors, which operate as permeable-base transistors. By introducing vanadium oxide (V2O5) between the injecting metal and NPB layer at the transistor emitter, we reduced the emitter operational voltage.

Ambipolar permeable metal-base transistor based on NPB/C-60 heterojunction

In this paper, we report the fabrication of permeable metal-base organic transistors based on N,N'-diphenyl-N,N'-bis(1-naphthylphenyl)-1,1'-biphenyl-4,4'-diamine (NPB)/C-60 heterojunction as both emitter and collector. By applying different polarities of voltage bias to the collector and the base, and input current to the emitter, the ambipolar behavior can be observed. The device demonstrates excellent common-base characteristics both in P-type and N-type modes with common-base current gains of 0.998 and 0.999, respectively.

Organic Thin-Film Transistor Memory With Nanoparticle Floating Gate

Organic thin-film transistor memory devices were realized by inserting a layer of nanoparticles (such as Ag or CaF2) between two Nylon 6 gate dielectrics as the floating gate. The transistor memories were fabricated on glass substrates by full thermal deposition. The transistors exhibit significant hysteresis behavior in current-voltage characteristics, due to the separated Ag or CaF2 nanoparticle islands that act as charge trap centers. The mechanism of the transistor memory operation was discussed.

Micropatterning of metal films coated on polymer surfaces with epoxy mold and its application to organic field effect transistor fabrication

In this letter, a simple and versatile approach to micropatterning a metal film, which is evaporated on a Si substrate coated with polymer, is demonstrated by the use of a prepatterned epoxy mold. The polymer interlayer between the metal and the Si substrate is found important for the high quality pattern. When the metal-polymer-Si sandwich structure is heated with the temperature below T-m but above T-g of the polymer, the plastic deformation of the polymer film occurs under sufficiently high pressure applied. It causes the metal to crack locally or weaken along the pattern edges. Further heating while applying a lower pressure results in the formation of an intimate junction between the epoxy stamp and the metal film. Under these conditions the epoxy cures further, ensuring adhesion between the stamp and the film. The lift-off process works because the adhesion between the epoxy and the metal film is stronger than that between the metal film and the polymer. A polymer field effect transistor is fabricated in order to demonstrate potential applications of this micropatterning approach.