A novel FPGA-based evolvable hardware system based on multiple processing arrays

In this paper, an architecture based on a scalable and flexible set of Evolvable Processing arrays is presented. FPGA-native Dynamic Partial Reconfiguration (DPR) is used for evolution, which is done intrinsically, letting the system to adapt autonomously to variable run-time conditions, including the presence of transient and permanent faults. The architecture supports different modes of operation, namely: independent, parallel, cascaded or bypass mode. These modes of operation can be used during evolution time or during normal operation. The evolvability of the architecture is combined with fault-tolerance techniques, to enhance the platform with self-healing features, making it suitable for applications which require both high adaptability and reliability. Experimental results show that such a system may benefit from accelerated evolution times, increased performance and improved dependability, mainly by increasing fault tolerance for transient and permanent faults, as well as providing some fault identification possibilities. The evolvable HW array shown is tailored for window-based image processing applications.

Plataforma de Integración Hardware-Software para Testbed de Redes de Sensores Inalámbricas

El campo de las redes de sensores inalámbricas ha cobrado gran importancia en esta última década ya que se han abierto diversas líneas de investigación con el fin de poder llevar a la práctica los conceptos y definiciones que envuelven el potencial de esta tecnología, y que está llamada a ser el futuro en la adquisición de datos de cualquier entorno físico de aplicación, mediante una herramienta basada en la autogestión y desatención durante largos periodos de tiempo, capacidad de tomar muestras cuando sea necesario a través de nodos sensores que se caractericen por el ahorro de energía y que puedan ser capaces de trabajar de forma autónoma durante meses, y que el carácter inalámbrico de la red a desplegar facilite las tareas de instalación y mantenimiento. Ello requiere que las condiciones para que una red de sensores inalámbrica sea la forma más viable de monitorizar un determinado entorno se base en ciertos requisitos de diseño, como lo es la baja tasa de transferencia de datos por parte de los nodos (estos deben ser capaces de transmitir la información recolectada desde los sensores y luego permanecer dormidos hasta una nueva adquisición), hardware enfocado al bajo consumo de energía con el fin de evitar cambios en la fuente de energía (baterías) durante largos periodos de tiempo, adaptabilidad al entorno de aplicación, flexibilidad y escalabilidad de la red si la aplicación hace necesario la inclusión de nuevos nodos o la modificación de los ya existentes, sin que ello suponga mayores dificultades en su desarrollo e implementación. El Centro de Electrónica industrial de la Universidad Politécnica de Madrid se incluye dentro de este último grupo, donde se ha diseñado una completa plataforma hardware para redes de sensores inalámbricas, con el fin de investigar las potencialidades, dificultades y retos que supone el realizar un despliegue de nodos inalámbricos en cumplimiento de características primordiales como autonomía, flexibilidad y escalabilidad de la red, además de la autogestión de los dispositivos que forman parte de ella. El presente trabajo de investigación se centra en cubrir estas necesidades, por lo que su principal objetivo es la creación de una plataforma de integración hardware-software que permita explotar todas las potencialidades de la arquitectura Cookies a través de una herramienta que facilite el despliegue, control y mantenimiento de una red de sensores inalámbrica, con el fin último de contar con un sistema total para el prototipado rápido de aplicaciones, soporte de pruebas de nuevos desarrollos y la posibilidad de implementación de dicha plataforma en cualquier entorno real, siendo sólo necesario realizar pequeños ajustes desde el más alto nivel de abstracción para que el sistema sea capaz de adaptarse por sí solo. Para cumplir tales propósitos y lograr una completa integración del sistema conjunto, ha sido necesario fijar principalmente tres líneas de trabajo que se enmarcan dentro de los objetivos específicos del presente proyecto, las cuales se detallan a continuación: Bibliotecas Software modulares: Basada en la filosofía de modularidad y flexibilidad de la plataforma hardware, se hace imprescindible primeramente contar con una plataforma software para el control de todos y cada uno de los elementos que componen al nodo Cookie, a partir de bloques funcionales que permitan gestionar desde el núcleo de procesamiento principal todas las características de la plataforma. Esto permitirá asegurar el control de los recursos hardware y facilitar la utilización de la plataforma desde un nivel más alto de abstracción, sólo con la configuración de parámetros estandarizados para el funcionamiento de la misma. Perfil de aplicación Cookies: Después de contar con bloques software que permitan controlar las características de bajo nivel del nodo inalámbrico, es necesario crear una herramienta para la estandarización de la forma en la que se comunican los dispositivos a nivel de aplicación, con el fin de gestionar las características y atributos de los nodos sensores de forma remota y facilitar el entendimiento entre ellos. Para ello, es necesario fijar ciertas directivas y reglas que permitan homogeneizar la gestión de tareas asociadas a los nodos Cookies, a través del diseño de un perfil de aplicación. Testbed para redes de sensores: Como resultado de las dos líneas anteriores de trabajo, la idea es contar con un instrumento que permita realizar pruebas reales haciendo uso de la plataforma de integración HW-SW, a partir de la gestión de todas las características y potencialidades que ofrece el perfil de aplicación creado y así facilitar el desarrollo de prototipos para aplicaciones basadas en redes de sensores inalámbricas, de forma rápida y eficiente. En este sentido, la idea es contar con un banco de pruebas basado en un despliegue de nodos Cookies que pueda ser controlado desde un ordenador central a través de una interfaz de usuario, desde el cual se lleva a cabo la monitorización y actuación sobre la red inalámbrica. Con el fin de lograr todos los objetivos planteados, ha sido necesario realizar un exhaustivo estudio de la plataforma hardware descrita anteriormente con el fin de conocer la forma en la que interactúan cada uno de los elementos incluidos en los nodos, así como la arquitectura y filosofía de los mismos, para poder llevar a cabo la integración con el software y, como se verá más adelante, realizar ajustes en el hardware para poder implementar correctamente las funcionalidades diseñadas. Por otro lado, ha sido necesario analizar las características de la especificación ZigBee y, sobre todo, las propiedades que posee el módulo de comunicaciones que incluye la plataforma hardware, el ETRX2, con el fin de poder realizar una configuración y gestión adecuada de los nodos a través de la red inalámbrica, aprovechando las posibilidades y recursos que ofrece dicho módulo.

Instrumentation for accelerated life tests of concentrator solar cells

Concentrator photovoltaic is an emergent technology that may be a good economical and efficient alternative for the generation of electricity at a competitive cost. However, the reliability of these new solar cells and systems is still an open issue due to the high-irradiation level they are subjected to as well as the electrical and thermal stresses that they are expected to endure. To evaluate the reliability in a short period of time, accelerated aging tests are essential. Thermal aging tests for concentrator photovoltaic solar cells and systems under illumination are not available because no technical solution to the problem of reaching the working concentration inside a climatic chamber has been available. This work presents an automatic instrumentation system that overcomes the aforementioned limitation. Working conditions have been simulated by forward biasing the solar cells to the current they would handle at the working concentration (in this case, 700 and 1050 times the irradiance at one standard sun). The instrumentation system has been deployed for more than 10 000 h in a thermal aging test for III-V concentrator solar cells, in which the generated power evolution at different temperatures has been monitored. As a result of this test, the acceleration factor has been calculated, thus allowing for the degradation evolution at any temperature in addition to normal working conditions to be obtained.

NDT for concrete under accelerated freeze/thaw tests and surface scaling

Freezing of water or salt solution in concrete pores is a main cause for severe damage and significant reduction of the service life. Most of the freeze-thaw (F-T) accelerated tests measure the scaling of concrete by weighting. This paper presents complementary procedures based on the use of strain gages and ultrasonic pulse velocity (UPV) for measuring the deterioration of concrete due to freezing and thawing. These non-destructive testing (NDT) procedures are applied to two types of concretes, one susceptible to F-T damage and the other does not. The results show a good correlation between scaling and the measurements obtained with NDT. Showing NDT the advantage to detect before the damage and to perform continuous measurement

Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems

This paper presents an analysis of the fault tolerance achieved by an autonomous, fully embedded evolvable hardware system, which uses a combination of partial dynamic reconfiguration and an evolutionary algorithm (EA). It demonstrates that the system may self-recover from both transient and cumulative permanent faults. This self-adaptive system, based on a 2D array of 16 (4×4) Processing Elements (PEs), is tested with an image filtering application. Results show that it may properly recover from faults in up to 3 PEs, that is, more than 18% cumulative permanent faults. Two fault models are used for testing purposes, at PE and CLB levels. Two self-healing strategies are also introduced, depending on whether fault diagnosis is available or not. They are based on scrubbing, fitness evaluation, dynamic partial reconfiguration and in-system evolutionary adaptation. Since most of these adaptability features are already available on the system for its normal operation, resource cost for self-healing is very low (only some code additions in the internal microprocessor core)

Inner-Hair Cells Parameterized-Hardware Implementation for Personalized Auditory Nerve Stimulation

In this paper the hardware implementation of an inner hair cell model is presented. Main features of the design are the use of Meddis’ transduction structure and the methodology for Design with Reusability. Which allows future migration to new hardware and design refinements for speech processing and custom-made hearing aids

Accelerated life test of high luminosity AlGaInP LEDs

Specific tests to assess reliability of high luminosity AlInGaP LED for outdoor applications are needed. In this paper tests to propose a model involving three parameters: temperature, humidity and current have been carried out. Temperature, humidity and current accelerated model has been proposed to evaluate the reliability of this type of LED. Degradation and catastrophic failure mechanisms have been analyzed. Finally we analyze the effect of serial resistance in power luminosity degradation.

Including hardware/software co-design in the ASSERT model driven engineering process.

Abstract. The ASSERT project de?ned new software engineering methods and tools for the development of critical embedded real-time systems in the space domain. The ASSERT model-driven engineering process was one of the achievements of the project and is based on the concept of property- preserving model transformations. The key element of this process is that non-functional properties of the software system must be preserved during model transformations. Properties preservation is carried out through model transformations compliant with the Ravenscar Pro?le and provides a formal basis to the process. In this way, the so-called Ravenscar Computational Model is central to the whole ASSERT process. This paper describes the work done in the HWSWCO study, whose main objective has been to address the integration of the Hardware/Software co-design phase in the ASSERT process. In order to do that, non-functional properties of the software system must also be preserved during hardware synthesis. Keywords : Ada 2005, Ravenscar pro?le, Hardware/Software co-design, real- time systems, high-integrity systems, ORK

Hardware Reuse Improvement through the Domain Specific Language dHDL.

The dHDL language has been defined to improve hardware design productivity. This is achieved through the definition of a better reuse interface (including parameters, attributes and macroports) and the creation of control structures that help the designer in the hardware generation process.

Improving Hardware Reuse through XML-based Interface Encapsulation

This work proposes an encapsulation scheme aimed at simplifying the reuse process of hardware cores. This hardware encapsulation approach has been conceived with a twofold objective. First, we look for the improvement of the reuse interface associated with the hardware core description. This is carried out in a first encapsulation level by improving the limited types and configuration options available in the conventional HDLs interface, and also providing information related to the implementation itself. Second, we have devised a more generic interface focused on describing the function avoiding details from a particular implementation, what corresponds to a second encapsulation level. This encapsulation allows the designer to define how to configure and use the design to implement a given functionality. The proposed encapsulation schemes help improving the amount of information that can be supplied with the design, and also allow to automate the process of searching, configuring and implementing diverse alternatives.

Preliminary temperature Accelerated Life Test (ALT) on III-V commercial concentrator triple-junction solar cells

A quantitative temperature accelerated life test on sixty GaInP/GaInAs/Ge triple-junction commercial concentrator solar cells is being carried out. The final objective of this experiment is to evaluate the reliability, warranty period, and failure mechanism of high concentration solar cells in a moderate period of time. The acceleration of the degradation is realized by subjecting the solar cells at temperatures markedly higher than the nominal working temperature under a concentrator Three experiments at three different temperatures are necessary in order to obtain the acceleration factor which relates the time at the stress level with the time at nominal working conditions. . However, up to now only the test at the highest temperature has finished. Therefore, we can not provide complete reliability information but we have analyzed the life data and the failure mode of the solar cells inside the climatic chamber at the highest temperature. The failures have been all of them catastrophic. In fact, the solar cells have turned into short circuits. We have fitted the failure distribution to a two parameters Weibull function. The failures are wear-out type. We have observed that the busbar and the surrounding fingers are completely deteriorate

The DLMT hardware implementation. A comparative study with the DCT and the DWT

In the last recent years, with the popularity of image compression techniques, many architectures have been proposed. Those have been generally based on the Forward and Inverse Discrete Cosine Transform (FDCT, IDCT). Alternatively, compression schemes based on discrete "wavelets" transform (DWT), used, both, in JPEG2000 coding standard and in H264-SVC (Scalable Video Coding) standard, do not need to divide the image into non-overlapping blocks or macroblocks. This paper discusses the DLMT (Discrete Lopez-Moreno Transform) hardware implementation. It proposes a new scheme intermediate between the DCT and the DWT, comparing results of the most relevant proposed architectures for benchmarking. The DLMT can also be applied over a whole image, but this does not involve increasing computational complexity. FPGA implementation results show that the proposed DLMT has significant performance benefits and improvements comparing with the DCT and the DWT and consequently it is very suitable for implementation on WSN (Wireless Sensor Network) applications.

On the automatic integration of hardware accelerators into FPGA-based embedded systems

This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Hardware-software integration platform for a WSN testbed based on cookies nodes

In this work a complete hardware-software support platform for a WSN testbed focused on developing wireless sensor applications in a simple and intuitive way is presented, as an alternative of commercial-motes-based testbeds that can be found in the state of the art. The main target of this hardware-software platform is to provide the highest abstraction level on the management of WSNs but in the simplest way in order to achieve a fast profiling mechanism for reliable prototyping based on the Cookies platform as well as helping users to develop, test and validate Cookie-Based WSN applications.

A hardware in the loop design methodology for FPGA system and its application to complex functions

In this work, a unified algorithm-architecture-circuit co-design environment for complex FPGA system development is presented. The main objective is to find an efficient methodology for designing a configurable optimized FPGA system by using as few efforts as possible in verification stage, so as to speed up the development period. A proposed high performance FFT/iFFT processor for Multiband Orthogonal Frequency Division Multiplexing Ultra Wideband (MB-OFDM UWB) system design process is given as an example to demonstrate the proposed methodology. This efficient design methodology is tested and considered to be suitable for almost all types of complex FPGA system designs and verifications.