Uncovering cold disruption of the circadian clock in poplar

Dormancy is an adaptive mechanism that allows woody plants to survive at low temperatures during the winter. Disruption of circadian clock genes in winter or under low temperatures, both in long days as in short days, were described in our group few years ago (Ramos et al., 2005). Basic mechanisms of the circadian clock function are similar in herbaceous as well as in woody plants although there are differences in their response to low temperatures (Bieniawska et al., 2008). Woody plants growing in daylight conditions should have a specific transcriptional control above the circadian clock genes, which is responsible of their constitutive transcriptional activation observed under low temperatures conditions. In order to understand this regulatory process, we are analyzing the behavior of a circadian clock gene in poplar. To this aim, we have isolated its promoter region and fused to the luciferase reporter gene. This construct has been transformed into Populus tremula x P. alba 717-1B4 INRA clone. Here we present the characterization of these transgenic lines under different conditions of light and temperature.

New definitions of margin for multi-class Boosting algorithms

La familia de algoritmos de Boosting son un tipo de técnicas de clasificación y regresión que han demostrado ser muy eficaces en problemas de Visión Computacional. Tal es el caso de los problemas de detección, de seguimiento o bien de reconocimiento de caras, personas, objetos deformables y acciones. El primer y más popular algoritmo de Boosting, AdaBoost, fue concebido para problemas binarios. Desde entonces, muchas han sido las propuestas que han aparecido con objeto de trasladarlo a otros dominios más generales: multiclase, multilabel, con costes, etc. Nuestro interés se centra en extender AdaBoost al terreno de la clasificación multiclase, considerándolo como un primer paso para posteriores ampliaciones. En la presente tesis proponemos dos algoritmos de Boosting para problemas multiclase basados en nuevas derivaciones del concepto margen. El primero de ellos, PIBoost, está concebido para abordar el problema descomponiéndolo en subproblemas binarios. Por un lado, usamos una codificación vectorial para representar etiquetas y, por otro, utilizamos la función de pérdida exponencial multiclase para evaluar las respuestas. Esta codificación produce un conjunto de valores margen que conllevan un rango de penalizaciones en caso de fallo y recompensas en caso de acierto. La optimización iterativa del modelo genera un proceso de Boosting asimétrico cuyos costes dependen del número de etiquetas separadas por cada clasificador débil. De este modo nuestro algoritmo de Boosting tiene en cuenta el desbalanceo debido a las clases a la hora de construir el clasificador. El resultado es un método bien fundamentado que extiende de manera canónica al AdaBoost original. El segundo algoritmo propuesto, BAdaCost, está concebido para problemas multiclase dotados de una matriz de costes. Motivados por los escasos trabajos dedicados a generalizar AdaBoost al terreno multiclase con costes, hemos propuesto un nuevo concepto de margen que, a su vez, permite derivar una función de pérdida adecuada para evaluar costes. Consideramos nuestro algoritmo como la extensión más canónica de AdaBoost para este tipo de problemas, ya que generaliza a los algoritmos SAMME, Cost-Sensitive AdaBoost y PIBoost. Por otro lado, sugerimos un simple procedimiento para calcular matrices de coste adecuadas para mejorar el rendimiento de Boosting a la hora de abordar problemas estándar y problemas con datos desbalanceados. Una serie de experimentos nos sirven para demostrar la efectividad de ambos métodos frente a otros conocidos algoritmos de Boosting multiclase en sus respectivas áreas. En dichos experimentos se usan bases de datos de referencia en el área de Machine Learning, en primer lugar para minimizar errores y en segundo lugar para minimizar costes. Además, hemos podido aplicar BAdaCost con éxito a un proceso de segmentación, un caso particular de problema con datos desbalanceados. Concluimos justificando el horizonte de futuro que encierra el marco de trabajo que presentamos, tanto por su aplicabilidad como por su flexibilidad teórica. Abstract The family of Boosting algorithms represents a type of classification and regression approach that has shown to be very effective in Computer Vision problems. Such is the case of detection, tracking and recognition of faces, people, deformable objects and actions. The first and most popular algorithm, AdaBoost, was introduced in the context of binary classification. Since then, many works have been proposed to extend it to the more general multi-class, multi-label, costsensitive, etc... domains. Our interest is centered in extending AdaBoost to two problems in the multi-class field, considering it a first step for upcoming generalizations. In this dissertation we propose two Boosting algorithms for multi-class classification based on new generalizations of the concept of margin. The first of them, PIBoost, is conceived to tackle the multi-class problem by solving many binary sub-problems. We use a vectorial codification to represent class labels and a multi-class exponential loss function to evaluate classifier responses. This representation produces a set of margin values that provide a range of penalties for failures and rewards for successes. The stagewise optimization of this model introduces an asymmetric Boosting procedure whose costs depend on the number of classes separated by each weak-learner. In this way the Boosting procedure takes into account class imbalances when building the ensemble. The resulting algorithm is a well grounded method that canonically extends the original AdaBoost. The second algorithm proposed, BAdaCost, is conceived for multi-class problems endowed with a cost matrix. Motivated by the few cost-sensitive extensions of AdaBoost to the multi-class field, we propose a new margin that, in turn, yields a new loss function appropriate for evaluating costs. Since BAdaCost generalizes SAMME, Cost-Sensitive AdaBoost and PIBoost algorithms, we consider our algorithm as a canonical extension of AdaBoost to this kind of problems. We additionally suggest a simple procedure to compute cost matrices that improve the performance of Boosting in standard and unbalanced problems. A set of experiments is carried out to demonstrate the effectiveness of both methods against other relevant Boosting algorithms in their respective areas. In the experiments we resort to benchmark data sets used in the Machine Learning community, firstly for minimizing classification errors and secondly for minimizing costs. In addition, we successfully applied BAdaCost to a segmentation task, a particular problem in presence of imbalanced data. We conclude the thesis justifying the horizon of future improvements encompassed in our framework, due to its applicability and theoretical flexibility.

Desarrollo de estructuras nanofotonicas de campo cercano para intensificacion localizada de luz en celulas solares de banda intermedia - Near-field nanophotonic structures for localized light enhancement in intermediate band solar cells

This doctoral thesis explores some of the possibilities that near-field optics can bring to photovoltaics, and in particular to quantum-dot intermediate band solar cells (QD-IBSCs). Our main focus is the analytical optimization of the electric field distribution produced in the vicinity of single scattering particles, in order to produce the highest possible absorption enhancement in the photovoltaic medium in their surroundings. Near-field scattering structures have also been fabricated in laboratory, allowing the application of the previously studied theoretical concepts to real devices. We start by looking into the electrostatic scattering regime, which is only applicable to sub-wavelength sized particles. In this regime it was found that metallic nano-spheroids can produce absorption enhancements of about two orders of magnitude on the material in their vicinity, due to their strong plasmonic resonance. The frequency of such resonance can be tuned with the shape of the particles, allowing us to match it with the optimal transition energies of the intermediate band material. Since these metallic nanoparticles (MNPs) are to be inserted inside the cell photovoltaic medium, they should be coated by a thin insulating layer to prevent electron-hole recombination at their surface. This analysis is then generalized, using an analytical separation-of-variables method implemented in Mathematica7.0, to compute scattering by spheroids of any size and material. This code allowed the study of the scattering properties of wavelengthsized particles (mesoscopic regime), and it was verified that in this regime dielectric spheroids perform better than metallic. The light intensity scattered from such dielectric spheroids can have more than two orders of magnitude than the incident intensity, and the focal region in front of the particle can be shaped in several ways by changing the particle geometry and/or material. Experimental work was also performed in this PhD to implement in practice the concepts studied in the analysis of sub-wavelength MNPs. A wet-coating method was developed to self-assemble regular arrays of colloidal MNPs on the surface of several materials, such as silicon wafers, amorphous silicon films, gallium arsenide and glass. A series of thermal and chemical tests have been performed showing what treatments the nanoparticles can withstand for their embedment in a photovoltaic medium. MNPs arrays are then inserted in an amorphous silicon medium to study the effect of their plasmonic near-field enhancement on the absorption spectrum of the material. The self-assembled arrays of MNPs constructed in these experiments inspired a new strategy for fabricating IBSCs using colloidal quantum dots (CQDs). Such CQDs can be deposited in self-assembled monolayers, using procedures similar to those developed for the patterning of colloidal MNPs. The use of CQDs to form the intermediate band presents several important practical and physical advantages relative to the conventional dots epitaxially grown by the Stranski-Krastanov method. Besides, this provides a fast and inexpensive method for patterning binary arrays of QDs and MNPs, envisioned in the theoretical part of this thesis, in which the MNPs act as antennas focusing the light in the QDs and therefore boosting their absorption

Power Measurement Methodology for FPGA Devices

The efficiency of power optimization tools depends on information on design power provided by the power estimation models. Power models targeting different power groups can enable fast identification of the most power consuming parts of design and their properties. The accuracy of these estimation models is highly dependent on the accuracy of the method used for their characterization. The highest precision is achieved by using physical onboard measurements. In this paper, we present a measurement methodology that is primarily aimed at calibrating and validating high-level dynamic power estimation models. The measurements have been carefully designed to enable the separation of the interconnect power from the logic power and the power of the clock circuitry, so that each of these power groups can be used for the corresponding model validation. The standard measurement uncertainty is lower than 2% of the measured value even with a very small number of repeated measurements. Additionally, the accuracy of a commercial low-level power estimation tool has been also assessed for comparison purposes. The results indicate that the tool is not suitable for power estimation of data path-oriented designs.

Performance of Scheduling Policies in Adversarial Networks with Non-synchronized Clocks

In this paper we generalize the Continuous Adversarial Queuing Theory (CAQT) model (Blesa et al. in MFCS, Lecture Notes in Computer Science, vol. 3618, pp. 144–155, 2005) by considering the possibility that the router clocks in the network are not synchronized. We name the new model Non Synchronized CAQT (NSCAQT). Clearly, this new extension to the model only affects those scheduling policies that use some form of timing. In a first approach we consider the case in which although not synchronized, all clocks run at the same speed, maintaining constant differences. In this case we show that all universally stable policies in CAQT that use the injection time and the remaining path to schedule packets remain universally stable. These policies include, for instance, Shortest in System (SIS) and Longest in System (LIS). Then, we study the case in which clock differences can vary over time, but the maximum difference is bounded. In this model we show the universal stability of two families of policies related to SIS and LIS respectively (the priority of a packet in these policies depends on the arrival time and a function of the path traversed). The bounds we obtain in this case depend on the maximum difference between clocks. This is a necessary requirement, since we also show that LIS is not universally stable in systems without bounded clock difference. We then present a new policy that we call Longest in Queues (LIQ), which gives priority to the packet that has been waiting the longest in edge queues. This policy is universally stable and, if clocks maintain constant differences, the bounds we prove do not depend on them. To finish, we provide with simulation results that compare the behavior of some of these policies in a network with stochastic injection of packets.

The introduction of teaching innovations into the traditional teaching of construction and building materials

The traditional teaching methods used for training civil engineers are currently being called into question as a result of the new knowledge and skills now required by the labor market. In addition, the European Higher Education Area is requesting that students be given a greater say in their learning. In the subject called Construction and Building Materials at the Civil Engineering School of the Universidad Politécnica de Madrid, a path was set three academic years ago to lead to an improvement in traditional teaching by introducing active methodologies. The innovations are based on cooperative learning, new technologies, and continuous assessment. The writers’ proposal is to offer their experience as a contribution to the debate on how students can be encouraged to acquire the skills currently demanded from a civil engineer, though not overlooking solid, top-quality training. From the outcomes obtained, it can be concluded that using new teaching techniques to supplement a traditional approach provides more opportunities for students to learn while boosting their motivation. In our case, the introduction of these changes has resulted in an increased pass rate of 29% on average, when such a figure is considered in the light of the mean value of passes during the last decade.

Low-resource synchronous coincidence processor for positron emission tomography

We developed a new FPGA-based method for coincidence detection in positronemissiontomography. The method requires low device resources and no specific peripherals in order to resolve coincident digital pulses within a time window of a few nanoseconds. This method has been validated with a low-end Xilinx Spartan-3E and provided coincidence resolutions lower than 6 ns. This resolution depends directly on the signal propagation properties of the target device and the maximum available clock frequency, therefore it is expected to improve considerably on higher-end FPGAs.

A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations

In this paper, a new countermeasure against power and electromagnetic (EM) Side Channel Attacks (SCA) on FPGA implemented cryptographic algorithms is proposed. This structure mainly focuses on a critical vulnerability, Early Evaluation, also known as Early Propagation Effect (EPE), which exists in most conventional SCA-hardened DPL (Dual-rail with Precharge Logic) solutions. The main merit of this proposal is that the EPE can be effectively prevented by using a synchronized non regular precharge network, which maintains identical routing between the original and mirror parts, where costs and design complexity compared with previous EPE-resistant countermeasures are reduced, while security level is not sacrificed. Another advantage for our Precharge Absorbed(PA) - DPL method is that its Dual-Core style (independent architecture for true and false parts) could be generated using partial reconfiguration. This helps to get a dynamic security protection with better energy planning. That means system only keeps the true part which fulfills the normal en/decryption task in low security level, and reconfigures the false parts once high security level is required. A relatively limited clock speed is a compromise, since signal propagation is restricted to a portion of the clock period. In this paper, we explain the principles of PA-DPL and provide the guidelines to design this structure. We experimentally validate our methods in a minimized AES co-processor on Xilinx Virtex-5 board using electromagnetic (EM) attacks.

Performance of Scheduling Policies in Adversarial Networks with Non-synchronized Clocks

In this paper we generalize the Continuous Adversarial Queuing Theory (CAQT) model (Blesa et al. in MFCS, Lecture Notes in Computer Science, vol. 3618, pp. 144–155, 2005) by considering the possibility that the router clocks in the network are not synchronized. We name the new model Non Synchronized CAQT (NSCAQT). Clearly, this new extension to the model only affects those scheduling policies that use some form of timing. In a first approach we consider the case in which although not synchronized, all clocks run at the same speed, maintaining constant differences. In this case we show that all universally stable policies in CAQT that use the injection time and the remaining path to schedule packets remain universally stable. These policies include, for instance, Shortest in System (SIS) and Longest in System (LIS). Then, we study the case in which clock differences can vary over time, but the maximum difference is bounded. In this model we show the universal stability of two families of policies related to SIS and LIS respectively (the priority of a packet in these policies depends on the arrival time and a function of the path traversed). The bounds we obtain in this case depend on the maximum difference between clocks. This is a necessary requirement, since we also show that LIS is not universally stable in systems without bounded clock difference. We then present a new policy that we call Longest in Queues (LIQ), which gives priority to the packet that has been waiting the longest in edge queues. This policy is universally stable and, if clocks maintain constant differences, the bounds we prove do not depend on them. To finish, we provide with simulation results that compare the behavior of some of these policies in a network with stochastic injection of packets.

Exploration of RVC applications using an ARM multicore processor = Exploración de aplicaciones RVC empleando un procesador ARM multinúcleo

Single core capabilities have reached their maximum clock speed; new multicore architectures provide an alternative way to tackle this issue instead. The design of decoding applications running on top of these multicore platforms and their optimization to exploit all system computational power is crucial to obtain best results. Since the development at the integration level of printed circuit boards are increasingly difficult to optimize due to physical constraints and the inherent increase in power consumption, development of multiprocessor architectures is becoming the new Holy Grail. In this sense, it is crucial to develop applications that can run on the new multi-core architectures and find out distributions to maximize the potential use of the system. Today most of commercial electronic devices, available in the market, are composed of embedded systems. These devices incorporate recently multi-core processors. Task management onto multiple core/processors is not a trivial issue, and a good task/actor scheduling can yield to significant improvements in terms of efficiency gains and also processor power consumption. Scheduling of data flows between the actors that implement the applications aims to harness multi-core architectures to more types of applications, with an explicit expression of parallelism into the application. On the other hand, the recent development of the MPEG Reconfigurable Video Coding (RVC) standard allows the reconfiguration of the video decoders. RVC is a flexible standard compatible with MPEG developed codecs, making it the ideal tool to integrate into the new multimedia terminals to decode video sequences. With the new versions of the Open RVC-CAL Compiler (Orcc), a static mapping of the actors that implement the functionality of the application can be done once the application executable has been generated. This static mapping must be done for each of the different cores available on the working platform. It has been chosen an embedded system with a processor with two ARMv7 cores. This platform allows us to obtain the desired tests, get as much improvement results from the execution on a single core, and contrast both with a PC-based multiprocessor system. Las posibilidades ofrecidas por el aumento de la velocidad de la frecuencia de reloj de sistemas de un solo procesador están siendo agotadas. Las nuevas arquitecturas multiprocesador proporcionan una vía de desarrollo alternativa en este sentido. El diseño y optimización de aplicaciones de descodificación de video que se ejecuten sobre las nuevas arquitecturas permiten un mejor aprovechamiento y favorecen la obtención de mayores rendimientos. Hoy en día muchos de los dispositivos comerciales que se están lanzando al mercado están integrados por sistemas embebidos, que recientemente están basados en arquitecturas multinúcleo. El manejo de las tareas de ejecución sobre este tipo de arquitecturas no es una tarea trivial, y una buena planificación de los actores que implementan las funcionalidades puede proporcionar importantes mejoras en términos de eficiencia en el uso de la capacidad de los procesadores y, por ende, del consumo de energía. Por otro lado, el reciente desarrollo del estándar de Codificación de Video Reconfigurable (RVC), permite la reconfiguración de los descodificadores de video. RVC es un estándar flexible y compatible con anteriores codecs desarrollados por MPEG. Esto hace de RVC el estándar ideal para ser incorporado en los nuevos terminales multimedia que se están comercializando. Con el desarrollo de las nuevas versiones del compilador específico para el desarrollo de lenguaje RVC-CAL (Orcc), en el que se basa MPEG RVC, el mapeo estático, para entornos basados en multiprocesador, de los actores que integran un descodificador es posible. Se ha elegido un sistema embebido con un procesador con dos núcleos ARMv7. Esta plataforma nos permitirá llevar a cabo las pruebas de verificación y contraste de los conceptos estudiados en este trabajo, en el sentido del desarrollo de descodificadores de video basados en MPEG RVC y del estudio de la planificación y mapeo estático de los mismos.

Oscillatory genetic circuits: new designs and mathematical models

Introduction and motivation: A wide variety of organisms have developed in-ternal biomolecular clocks in order to adapt to cyclic changes of the environment. Clock operation involves genetic networks. These genetic networks have to be mod¬eled in order to understand the underlying mechanism of oscillations and to design new synthetic cellular clocks. This doctoral thesis has resulted in two contributions to the fields of genetic clocks and systems and synthetic biology, generally. The first contribution is a new genetic circuit model that exhibits an oscillatory behav¬ior through catalytic RNA molecules. The second and major contribution is a new genetic circuit model demonstrating that a repressor molecule acting on the positive feedback of a self-activating gene produces reliable oscillations. First contribution: A new model of a synthetic genetic oscillator based on a typical two-gene motif with one positive and one negative feedback loop is pre¬sented. The originality is that the repressor is a catalytic RNA molecule rather than a protein or a non-catalytic RNA molecule. This catalytic RNA is a ribozyme that acts post-transcriptionally by binding to and cleaving target mRNA molecules. This genetic clock involves just two genes, a mRNA and an activator protein, apart from the ribozyme. Parameter values that produce a circadian period in both determin¬istic and stochastic simulations have been chosen as an example of clock operation. The effects of the stochastic fluctuations are quantified by a period histogram and autocorrelation function. The conclusion is that catalytic RNA molecules can act as repressor proteins and simplify the design of genetic oscillators. Second and major contribution: It is demonstrated that a self-activating gene in conjunction with a simple negative interaction can easily produce robust matically validated. This model is comprised of two clearly distinct parts. The first is a positive feedback created by a protein that binds to the promoter of its own gene and activates the transcription. The second is a negative interaction in which a repressor molecule prevents this protein from binding to its promoter. A stochastic study shows that the system is robust to noise. A deterministic study identifies that the oscillator dynamics are mainly driven by two types of biomolecules: the protein, and the complex formed by the repressor and this protein. The main conclusion of this study is that a simple and usual negative interaction, such as degradation, se¬questration or inhibition, acting on the positive transcriptional feedback of a single gene is a sufficient condition to produce reliable oscillations. One gene is enough and the positive transcriptional feedback signal does not need to activate a second repressor gene. At the genetic level, this means that an explicit negative feedback loop is not necessary. Unlike many genetic oscillators, this model needs neither cooperative binding reactions nor the formation of protein multimers. Applications and future research directions: Recently, RNA molecules have been found to play many new catalytic roles. The first oscillatory genetic model proposed in this thesis uses ribozymes as repressor molecules. This could provide new synthetic biology design principles and a better understanding of cel¬lular clocks regulated by RNA molecules. The second genetic model proposed here involves only a repression acting on a self-activating gene and produces robust oscil¬lations. Unlike current two-gene oscillators, this model surprisingly does not require a second repressor gene. This result could help to clarify the design principles of cellular clocks and constitute a new efficient tool for engineering synthetic genetic oscillators. Possible follow-on research directions are: validate models in vivo and in vitro, research the potential of second model as a genetic memory, investigate new genetic oscillators regulated by non-coding RNAs and design a biosensor of positive feedbacks in genetic networks based on the operation of the second model Resumen Introduccion y motivacion: Una amplia variedad de organismos han desarro-llado relojes biomoleculares internos con el fin de adaptarse a los cambios ciclicos del entorno. El funcionamiento de estos relojes involucra redes geneticas. El mo delado de estas redes geneticas es esencial tanto para entender los mecanismos que producen las oscilaciones como para diseiiar nuevos circuitos sinteticos en celulas. Esta tesis doctoral ha dado lugar a dos contribuciones dentro de los campos de los circuitos geneticos en particular, y biologia de sistemas y sintetica en general. La primera contribucion es un nuevo modelo de circuito genetico que muestra un comportamiento oscilatorio usando moleculas de ARN cataliticas. La segunda y principal contribucion es un nuevo modelo de circuito genetico que demuestra que una molecula represora actuando sobre el lazo de un gen auto-activado produce oscilaciones robustas. Primera contribucion: Es un nuevo modelo de oscilador genetico sintetico basado en una tipica red genetica compuesta por dos genes con dos lazos de retroa-limentacion, uno positivo y otro negativo. La novedad de este modelo es que el represor es una molecula de ARN catalftica, en lugar de una protefna o una molecula de ARN no-catalitica. Este ARN catalitico es una ribozima que actua despues de la transcription genetica uniendose y cortando moleculas de ARN mensajero (ARNm). Este reloj genetico involucra solo dos genes, un ARNm y una proteina activadora, aparte de la ribozima. Como ejemplo de funcionamiento, se han escogido valores de los parametros que producen oscilaciones con periodo circadiano (24 horas) tanto en simulaciones deterministas como estocasticas. El efecto de las fluctuaciones es-tocasticas ha sido cuantificado mediante un histograma del periodo y la función de auto-correlacion. La conclusion es que las moleculas de ARN con propiedades cataliticas pueden jugar el misnio papel que las protemas represoras, y por lo tanto, simplificar el diseno de los osciladores geneticos. Segunda y principal contribucion: Es un nuevo modelo de oscilador genetico que demuestra que un gen auto-activado junto con una simple interaction negativa puede producir oscilaciones robustas. Este modelo ha sido estudiado y validado matematicamente. El modelo esta compuesto de dos partes bien diferenciadas. La primera parte es un lazo de retroalimentacion positiva creado por una proteina que se une al promotor de su propio gen activando la transcription. La segunda parte es una interaction negativa en la que una molecula represora evita la union de la proteina con el promotor. Un estudio estocastico muestra que el sistema es robusto al ruido. Un estudio determinista muestra que la dinamica del sistema es debida principalmente a dos tipos de biomoleculas: la proteina, y el complejo formado por el represor y esta proteina. La conclusion principal de este estudio es que una simple y usual interaction negativa, tal como una degradation, un secuestro o una inhibition, actuando sobre el lazo de retroalimentacion positiva de un solo gen es una condition suficiente para producir oscilaciones robustas. Un gen es suficiente y el lazo de retroalimentacion positiva no necesita activar a un segundo gen represor, tal y como ocurre en los relojes actuales con dos genes. Esto significa que a nivel genetico un lazo de retroalimentacion negativa no es necesario de forma explicita. Ademas, este modelo no necesita reacciones cooperativas ni la formation de multimeros proteicos, al contrario que en muchos osciladores geneticos. Aplicaciones y futuras lineas de investigacion: En los liltimos anos, se han descubierto muchas moleculas de ARN con capacidad catalitica. El primer modelo de oscilador genetico propuesto en esta tesis usa ribozimas como moleculas repre¬soras. Esto podria proporcionar nuevos principios de diseno en biologia sintetica y una mejor comprension de los relojes celulares regulados por moleculas de ARN. El segundo modelo de oscilador genetico propuesto aqui involucra solo una represion actuando sobre un gen auto-activado y produce oscilaciones robustas. Sorprendente-mente, un segundo gen represor no es necesario al contrario que en los bien conocidos osciladores con dos genes. Este resultado podria ayudar a clarificar los principios de diseno de los relojes celulares naturales y constituir una nueva y eficiente he-rramienta para crear osciladores geneticos sinteticos. Algunas de las futuras lineas de investigation abiertas tras esta tesis son: (1) la validation in vivo e in vitro de ambos modelos, (2) el estudio del potential del segundo modelo como circuito base para la construction de una memoria genetica, (3) el estudio de nuevos osciladores geneticos regulados por ARN no codificante y, por ultimo, (4) el rediseno del se¬gundo modelo de oscilador genetico para su uso como biosensor capaz de detectar genes auto-activados en redes geneticas.

A new feature extraction method for signal classification applied to cat spinal cord signals

In the spinal cord of the anesthetized cat, spontaneous cord dorsum potentials (CDPs) appear synchronously along the lumbo-sacral segments. These CDPs have different shapes and magnitudes. Previous work has indicated that some CDPs appear to be specially associated with the activation of spinal pathways that lead to primary afferent depolarization and presynaptic inhibition. Visual detection and classification of these CDPs provides relevant information on the functional organization of the neural networks involved in the control of sensory information and allows the characterization of the changes produced by acute nerve and spinal lesions. We now present a novel feature extraction approach for signal classification, applied to CDP detection. The method is based on an intuitive procedure. We first remove by convolution the noise from the CDPs recorded in each given spinal segment. Then, we assign a coefficient for each main local maximum of the signal using its amplitude and distance to the most important maximum of the signal. These coefficients will be the input for the subsequent classification algorithm. In particular, we employ gradient boosting classification trees. This combination of approaches allows a faster and more accurate discrimination of CDPs than is obtained by other methods.

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). Among previous EPE-resistant architectures, PA-DPL logic offers EPE-free capability at relatively low cost. However, its separate dual core structure is a weakness when facing concentrated EM attacks where a tiny EM probe can be precisely positioned closer to one of the two cores. In this paper, we present an PA-DPL dual-core interleaved structure to strengthen resistance against sophisticated EM attacks on Xilinx FPGA implementations. The main merit of the proposed structure is that every two routing in each signal pair are kept identical even the dual cores are interleaved together. By minimizing the distance between the complementary routings and instances of both cores, even the concentrated EM measurement cannot easily distinguish the minor EM field unbalance. In PA- DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. Regarding this, we made an improvement to extend the duty cycle of evaluation phase to more than 40 percent, yielding a larger maximum working frequency. The detailed design flow is also presented. We validate the security improvement against EM attack by implementing a simplified AES co-processor in Virtex-5 FPGA.

Development of Embedded Linux Applications Using ZedBoard

The purpose of this document is to create a modest integration guide for embedding a Linux Operating System on ZedBoard development platform, based on Xilinx’s Zynq-7000 All Programmable System on Chip which contains a dual core ARM Cortex-A9 and a 7 Series FPGA Artix-7. The integration process has been structured in four chapters according to the logic generation of the different parts that compose the embedded system. With the intention of automating the generation process of a complete Linux distribution specific for ZedBoard platform, BuildRoot development platform it is used. Once the embedding process finished, it was decided to add to the system the required functionalities for adding support for IEEE1588 Standard for Precision Clock Synchronization Protocol for Networked Measurement and Control Systems, through a user space Linux program which implements the protocol. That PTP user space implementation program has been cross-compiled, executed on target and tested for evaluating the functionalities added. RESUMEN El propósito de este documento es crear una modesta guía de integración de un sistema operativo Linux para la plataforma de desarrollo ZedBoard, basada en un System on Chip del fabricante Xilinx llamado Zynq-7000. Este System on Chip está compuesto por un procesador de doble núcleo ARM Cortex-A9 y una FPGA de la Serie 7 equiparable a una Artix-7. El proceso de integración se ha estructurado en cuatro grandes capítulos que se rigen según el orden lógico de generación de las distintas partes por las que el sistema empotrado está compuesto. Con el ánimo de automatizar el proceso de creación de una distribución de Linux específica para la plataforma ZedBoard, se ha utilizado la plataforma de desarrollo BuildRoot. Una vez terminado el proceso de integración del sistema empotrado, se procedió a dar dotar al sistema de las funcionalidades necesarias para dar soporte al estándar de sincronización de relojes en redes de área local, PTP IEEE1588, a través de una implementación del mismo en un programa de lado de usuario el cual ha sido compilado, ejecutado y testeado para evaluar el correcto funcionamiento de las funcionalidades añadidas.

Integración del descodificador OpenSVC en el DSP del OMAP3530

Hoy en día el uso de dispositivos portátiles multimedia es ya una realidad totalmente habitual. Además, estos dispositivos tienen una capacidad de cálculo y unos recursos gráficos y de memoria altos, tanto es así que por ejemplo en un móvil se pueden reproducir vídeos de muy alta calidad o tener capacidad para manejar entornos 3D. El precio del uso de estos recursos es un mayor consumo de batería que en ocasiones es demasiado alto y acortan en gran medida la vida de la carga útil de la batería. El Grupo de Diseño Electrónico y Microelectrónico de la Universidad Politécnica de Madrid ha abierto una línea de trabajo que busca la optimización del consumo de energía en este tipo de dispositivos, concretamente en el ámbito de la reproducción de vídeo. El enfoque para afrontar la solución del problema se basa en obtener un mayor rendimiento de la batería a costa de disminuir la experiencia multimedia del usuario. De esta manera, cuando la carga de la batería esté por debajo de un determinado umbral mientras el dispositivo esté reproduciendo un vídeo de alta calidad será el dispositivo quien se autoconfigure dinámicamente para consumir menos potencia en esta tarea, reduciendo la tasa de imágenes por segundo o la resolución del vídeo que se descodifica. Además de lo citado anteriormente se propone dividir la descodificación y la representación del vídeo en dos procesadores, uno de propósito general y otro para procesado digital de señal, con esto se consigue que tener la misma capacidad de cálculo que con un solo procesador pero a una frecuencia menor. Para materializar la propuesta se usará la tarjeta BeagleBoard basada en un procesador multinúcleo OMAP3530 de Texas Instrument que contiene dos núcleos: un ARM1 Cortex-A8 y un DSP2 de la familia C6000. Este procesador multinúcleo además permite modificar la frecuencia de reloj y la tensión de alimentación dinámicamente para conseguir reducir de este modo el consumo del terminal. Por otro lado, como reproductor de vídeos se utilizará una versión de MPlayer que integra un descodificador de vídeo escalable que permite elegir dinámicamente la resolución o las imágenes por segundo que se decodifican para posteriormente mostrarlas. Este reproductor se ejecutará en el núcleo ARM pero debido a la alta carga computacional de la descodificación de vídeos, y que el ARM no está optimizado para este tipo de procesado de datos, el reproductor debe encargar la tarea de la descodificación al DSP. El objetivo de este Proyecto Fin de Carrera consiste en que mientras el descodificador de vídeo está ejecutándose en el núcleo DSP y el Mplayer en el núcleo ARM del OMAP3530 se pueda elegir dinámicamente qué parte del vídeo se descodifica, es decir, seleccionar en tiempo real la calidad o capa del vídeo que se quiere mostrar. Haciendo esto, se podrá quitar carga computacional al núcleo ARM y asignársela al DSP el cuál puede procesarla a menor frecuencia para ahorrar batería. 1 ARM: Es una arquitectura de procesadores de propósito general basada en RISC (Reduced Instruction Set Computer). Es desarrollada por la empresa inglesa ARM holdings. 2 DSP: Procesador Digital de Señal (Digital Signal Processor). Es un sistema basado en procesador, el cual está orientado al cálculo matemático a altas velocidad. Generalmente poseen varias unidades aritmético-lógicas (ALUs) para conseguir realizar varias operaciones simultáneamente. SUMMARY. Nowadays, the use of multimedia devices is a well known reality. In addition, these devices have high graphics and calculus performance and a lot of memory as well. In instance, we can play high quality videos and 3D environments in a mobile phone. That kind of use may increase the device's power consumption and make shorter the battery duration. Electronic and Microelectronic Design Group of Technical University of Madrid has a research line which is looking for optimization of power consumption while these devices are playing videos. The solution of this trouble is based on taking more advantage of battery by decreasing multimedia user experience. On this way, when battery charge is under a threshold while device is playing a high quality video the device is going to configure itself dynamically in order to decrease its power consumption by decreasing frame per second rate, video resolution or increasing the noise in the decoded frame. It is proposed splitting decoding and representation tasks in two processors in order to have the same calculus capability with lower frecuency. The first one is specialized in digital signal processing and the other one is a general purpose processor. In order to materialize this proposal we will use a board called BeagleBoard which is based on a multicore processor called OMAP3530 from Texas Instrument. This processor includes two cores: ARM Cortex-A8 and a TMS320C64+ DSP core. Changing clock frequency and supply voltage is allowed by OMAP3530, we can decrease the power consumption on this way. On the other hand, MPlayer will be used as video player. It includes a scalable video decoder which let us changing dynamically the resolution or frames per second rate of the video in order to show it later. This player will be executed by ARM core but this is not optimized for this task, for that reason, DSP core will be used to decoding video. The target of this final career project is being able to choose which part of the video is decoded each moment while decoder is executed by DSP and Mplayer by ARM. It will be able to change in real time the video quality, resolution and frames per second that user want to show. On this way, reducing the computational charge within the processor will be possible.