On the automatic integration of hardware accelerators into FPGA-based embedded systems

This paper proposes an automatic framework for the seamless integration of hardware accelerators, starting from an OpenMP-based application and an XML file describing the HW/SW partitioning. It extends a fully software architecture by generating and integrating the cores, along with the proper interfaces, and the code for scheduling and synchronization. Experimental results show that it is possible to validate different solutions only by varying the input code.

Implementation techniques for evolvable HW systems: virtual vs. dynamic reconfiguration

Adaptive hardware requires some reconfiguration capabilities. FPGAs with native dynamic partial reconfiguration (DPR) support pose a dilemma for system designers: whether to use native DPR or to build a virtual reconfigurable circuit (VRC) on top of the FPGA which allows selecting alternative functions by a multiplexing scheme. This solution allows much faster reconfiguration, but with higher resource overhead. This paper discusses the advantages of both implementations for a 2D image processing matrix. Results show how higher operating frequency is obtained for the matrix using DPR. However, this is compensated in the VRC during evolution due to the comparatively negligible reconfiguration time. Regarding area, the DPR implementation consumes slightly more resources due to the reconfiguration engine, but adds further more capabilities to the system.

A self-adaptive image processing application based on evolvable and scalable hardware

Evolvable Hardware (EH) is a technique that consists of using reconfigurable hardware devices whose configuration is controlled by an Evolutionary Algorithm (EA). Our system consists of a fully-FPGA implemented scalable EH platform, where the Reconfigurable processing Core (RC) can adaptively increase or decrease in size. Figure 1 shows the architecture of the proposed System-on-Programmable-Chip (SoPC), consisting of a MicroBlaze processor responsible of controlling the whole system operation, a Reconfiguration Engine (RE), and a Reconfigurable processing Core which is able to change its size in both height and width. This system is used to implement image filters, which are generated autonomously thanks to the evolutionary process. The system is complemented with a camera that enables the usage of the platform for real time applications.

Run-time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs

Systems relying on fixed hardware components with a static level of parallelism can suffer from an underuse of logical resources, since they have to be designed for the worst-case scenario. This problem is especially important in video applications due to the emergence of new flexible standards, like Scalable Video Coding (SVC), which offer several levels of scalability. In this paper, Dynamic and Partial Reconfiguration (DPR) of modern FPGAs is used to achieve run-time variable parallelism, by using scalable architectures where the size can be adapted at run-time. Based on this proposal, a scalable Deblocking Filter core (DF), compliant with the H.264/AVC and SVC standards has been designed. This scalable DF allows run-time addition or removal of computational units working in parallel. Scalability is offered together with a scalable parallelization strategy at the macroblock (MB) level, such that when the size of the architecture changes, MB filtering order is modified accordingly

Thermal, stress, and traps effects in AlGaN/GaN HEMTs

GaN y AlN son materiales semiconductores piezoel��ctricos del grupo III-V. La heterouni��n AlGaN/GaN presenta una elevada carga de polarizaci��n tanto piezoel��ctrica como espont��nea en la intercara, lo que genera en su cercan��a un 2DEG de grandes concentraci��n y movilidad. Este 2DEG produce una muy alta potencia de salida, que a su vez genera una elevada temperatura de red. Las tensiones de puerta y drenador provocan un stress piezoel��ctrico inverso, que puede afectar a la carga de polarizaci��n piezoel��ctrica y as�� influir la densidad 2DEG y las caracter��sticas de salida. Por tanto, la f��sica del dispositivo es relevante para todos sus aspectos el��ctricos, t��rmicos y mec��nicos. En esta tesis se utiliza el software comercial COMSOL, basado en el m��todo de elementos finitos (FEM), para simular el comportamiento integral electro-t��rmico, electro-mec��nico y electro-t��rmico-mec��nico de los HEMTs de GaN. Las partes de acoplamiento incluyen el modelo de deriva y difusi��n para el transporte electr��nico, la conducci��n t��rmica y el efecto piezoel��ctrico. Mediante simulaciones y algunas caracterizaciones experimentales de los dispositivos, hemos analizado los efectos t��rmicos, de deformaci��n y de trampas. Se ha estudiado el impacto de la geometr��a del dispositivo en su auto-calentamiento mediante simulaciones electro-t��rmicas y algunas caracterizaciones el��ctricas. Entre los resultados m��s sobresalientes, encontramos que para la misma potencia de salida la distancia entre los contactos de puerta y drenador influye en generaci��n de calor en el canal, y as�� en su temperatura. El diamante posee une elevada conductividad t��rmica. Integrando el diamante en el dispositivo se puede dispersar el calor producido y as�� reducir el auto-calentamiento, al respecto de lo cual se han realizado diversas simulaciones electro-t��rmicas. Si la integraci��n del diamante es en la parte superior del transistor, los factores determinantes para la capacidad disipadora son el espesor de la capa de diamante, su conductividad t��rmica y su distancia a la fuente de calor. Este procedimiento de disipaci��n superior tambi��n puede reducir el impacto de la barrera t��rmica de intercara entre la capa adaptadora (buffer) y el substrato. La muy reducida conductividad el��ctrica del diamante permite que pueda contactar directamente el metal de puerta (muy cercano a la fuente de calor), lo que resulta muy conveniente para reducir el auto-calentamiento del dispositivo con polarizaci��n pulsada. Por otra parte se simul�� el dispositivo con diamante depositado en surcos atacados sobre el sustrato como caminos de disipaci��n de calor (disipador posterior). Aqu�� aparece una competencia de factores que influyen en la capacidad de disipaci��n, a saber, el surco atacado contribuye a aumentar la temperatura del dispositivo debido al peque��o tama��o del disipador, mientras que el diamante disminuir��a esa temperatura gracias a su elevada conductividad t��rmica. Por tanto, se precisan capas de diamante relativamente gruesas para reducer ele efecto de auto-calentamiento. Se compar�� la simulaci��n de la deformaci��n local en el borde de la puerta del lado cercano al drenador con estructuras de puerta est��ndar y con field plate, que podr��an ser muy relevantes respecto a fallos mec��nicos del dispositivo. Otras simulaciones se enfocaron al efecto de la deformaci��n intr��nseca de la capa de diamante en el comportamiento el��ctrico del dispositivo. Se han comparado los resultados de las simulaciones de la deformaci��n y las caracter��sticas el��ctricas de salida con datos experimentales obtenidos por espectroscop��a micro-Raman y medidas el��ctricas, respectivamente. Los resultados muestran el stress intr��nseco en la capa producido por la distribuci��n no uniforme del 2DEG en el canal y la regi��n de acceso. Adem��s de aumentar la potencia de salida del dispositivo, la deformaci��n intr��nseca en la capa de diamante podr��a mejorar la fiabilidad del dispositivo modulando la deformaci��n local en el borde de la puerta del lado del drenador. Finalmente, tambi��n se han simulado en este trabajo los efectos de trampas localizados en la superficie, el buffer y la barrera. Las medidas pulsadas muestran que tanto las puertas largas como las grandes separaciones entre los contactos de puerta y drenador aumentan el cociente entre la corriente pulsada frente a la corriente continua (lag ratio), es decir, disminuir el colapse de corriente (current collapse). Este efecto ha sido explicado mediante las simulaciones de los efectos de trampa de superficie. Por su parte, las referidas a trampas en el buffer se enfocaron en los efectos de atrapamiento din��mico, y su impacto en el auto-calentamiento del dispositivo. Se presenta tambi��n un modelo que describe el atrapamiento y liberaci��n de trampas en la barrera: mientras que el atrapamiento se debe a un t��nel directo del electr��n desde el metal de puerta, el desatrapamiento consiste en la emisi��n del electr��n en la banda de conducci��n mediante t��nel asistido por fonones. El modelo tambi��n simula la corriente de puerta, debida a la emisi��n electr��nica dependiente de la temperatura y el campo el��ctrico. Adem��s, tambi��n se ilustra la corriente de drenador dependiente de la temperatura y el campo el��ctrico. ABSTRACT GaN and AlN are group III-V piezoelectric semiconductor materials. The AlGaN/GaN heterojunction presents large piezoelectric and spontaneous polarization charge at the interface, leading to high 2DEG density close to the interface. A high power output would be obtained due to the high 2DEG density and mobility, which leads to elevated lattice temperature. The gate and drain biases induce converse piezoelectric stress that can influence the piezoelectric polarization charge and further influence the 2DEG density and output characteristics. Therefore, the device physics is relevant to all the electrical, thermal, and mechanical aspects. In this dissertation, by using the commercial finite-element-method (FEM) software COMSOL, we achieved the GaN HEMTs simulation with electro-thermal, electro-mechanical, and electro-thermo-mechanical full coupling. The coupling parts include the drift-diffusion model for the electron transport, the thermal conduction, and the piezoelectric effect. By simulations and some experimental characterizations, we have studied the device thermal, stress, and traps effects described in the following. The device geometry impact on the self-heating was studied by electro-thermal simulations and electrical characterizations. Among the obtained interesting results, we found that, for same power output, the distance between the gate and drain contact can influence distribution of the heat generation in the channel and thus influence the channel temperature. Diamond possesses high thermal conductivity. Integrated diamond with the device can spread the generated heat and thus potentially reduce the device self-heating effect. Electro-thermal simulations on this topic were performed. For the diamond integration on top of the device (top-side heat spreading), the determinant factors for the heat spreading ability are the diamond thickness, its thermal conductivity, and its distance to the heat source. The top-side heat spreading can also reduce the impact of thermal boundary resistance between the buffer and the substrate on the device thermal behavior. The very low electrical conductivity of diamond allows that it can directly contact the gate metal (which is very close to the heat source), being quite convenient to reduce the self-heating for the device under pulsed bias. Also, the diamond coated in vias etched in the substrate as heat spreading path (back-side heat spreading) was simulated. A competing mechanism influences the heat spreading ability, i.e., the etched vias would increase the device temperature due to the reduced heat sink while the coated diamond would decrease the device temperature due to its higher thermal conductivity. Therefore, relative thick coated diamond is needed in order to reduce the self-heating effect. The simulated local stress at the gate edge of the drain side for the device with standard and field plate gate structure were compared, which would be relevant to the device mechanical failure. Other stress simulations focused on the intrinsic stress in the diamond capping layer impact on the device electrical behaviors. The simulated stress and electrical output characteristics were compared to experimental data obtained by micro-Raman spectroscopy and electrical characterization, respectively. Results showed that the intrinsic stress in the capping layer caused the non-uniform distribution of 2DEG in the channel and the access region. Besides the enhancement of the device power output, intrinsic stress in the capping layer can potentially improve the device reliability by modulating the local stress at the gate edge of the drain side. Finally, the surface, buffer, and barrier traps effects were simulated in this work. Pulsed measurements showed that long gates and distances between gate and drain contact can increase the gate lag ratio (decrease the current collapse). This was explained by simulations on the surface traps effect. The simulations on buffer traps effects focused on illustrating the dynamic trapping/detrapping in the buffer and the self-heating impact on the device transient drain current. A model was presented to describe the trapping and detrapping in the barrier. The trapping was the electron direct tunneling from the gate metal while the detrapping was the electron emission into the conduction band described by phonon-assisted tunneling. The reverse gate current was simulated based on this model, whose mechanism can be attributed to the temperature and electric field dependent electron emission in the barrier. Furthermore, the mechanism of the device bias via the self-heating and electric field impact on the electron emission and the transient drain current were also illustrated.

A Dynamically Adaptable Bus Architecture for Trading-Off Among Performance, Consumption and Dependability in Cyber-Physical Systems

Cyber-Physical Systems need to handle increasingly complex tasks, which additionally, may have variable operating conditions over time. Therefore, dynamic resource management to adapt the system to different needs is required. In this paper, a new bus-based architecture, called ARTICo3, which by means of Dynamic Partial Reconfiguration, allows the replication of hardware tasks to support module redundancy, multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented. A configuration-aware data transaction unit permits data dispatching to more than one module in parallel, or provide coalesced data dispatching among different units to maximize the advantages of burst transactions. The selection of a given configuration is application independent but context-aware, which may be achieved by the combination of a multi-thread model similar to the CUDA kernel model specification, combined with a dynamic thread/task/kernel scheduler. A multi-kernel application for face recognition is used as an application example to show one scenario of the ARTICo3 architecture.

Dust effects on PV array performance: in-field observations with non-uniform patterns

This paper presents the impact of non-homogeneous deposits of dust on the performance of a PV array. The observations have been made in a 2-MW PV park in the southeast region of Spain. The results are that inhomogeneous dust leads to more significant consequences than the mere short-circuit current reduction resulting from transmittance losses. In particular, when the affected PV modules are part of a string together with other cleaned (or less dusty) ones, operation voltage losses arise. These voltage losses can be several times larger than the short-circuit ones, leading to power losses that can be much larger than what measurements suggest when the PV modules are considered separately. Significant hot-spot phenomena can also arise leading to cells exhibiting temperature differences of more than 20 degrees and thus representing a threat to the PV modules' lifetime.

Advanced Topics in Resource Analysis: Certification, Incrementality, Concurrency and Array-Sensitivity

El An��lisis de Consumo de Recursos o An��lisis de Coste trata de aproximar el coste de ejecutar un programa como una funci��n dependiente de sus datos de entrada. A pesar de que existen trabajos previos a esta tesis doctoral que desarrollan potentes marcos para el an��lisis de coste de programas orientados a objetos, algunos aspectos avanzados, como la eficiencia, la precisi��n y la fiabilidad de los resultados, todav��a deben ser estudiados en profundidad. Esta tesis aborda estos aspectos desde cuatro perspectivas diferentes: (1) Las estructuras de datos compartidas en la memoria del programa son una pesadilla para el an��lisis est��tico de programas. Trabajos recientes proponen una serie de condiciones de localidad para poder mantener de forma consistente informaci��n sobre los atributos de los objetos almacenados en memoria compartida, reemplazando ��stos por variables locales no almacenadas en la memoria compartida. En esta tesis presentamos dos extensiones a estos trabajos: la primera es considerar, no s��lo los accesos a los atributos, sino tambi��n los accesos a los elementos almacenados en arrays; la segunda se centra en los casos en los que las condiciones de localidad no se cumplen de forma incondicional, para lo cual, proponemos una t��cnica para encontrar las precondiciones necesarias para garantizar la consistencia de la informaci��n acerca de los datos almacenados en memoria. (2) El objetivo del an��lisis incremental es, dado un programa, los resultados de su an��lisis y una serie de cambios sobre el programa, obtener los nuevos resultados del an��lisis de la forma m��s eficiente posible, evitando reanalizar aquellos fragmentos de c��digo que no se hayan visto afectados por los cambios. Los analizadores actuales todav��a leen y analizan el programa completo de forma no incremental. Esta tesis presenta un an��lisis de coste incremental, que, dado un cambio en el programa, reconstruye la informaci��n sobre el coste del programa de todos los m��todos afectados por el cambio de forma incremental. Para esto, proponemos (i) un algoritmo multi-dominio y de punto fijo que puede ser utilizado en todos los an��lisis globales necesarios para inferir el coste, y (ii) una novedosa forma de almacenar las expresiones de coste que nos permite reconstruir de forma incremental ��nicamente las funciones de coste de aquellos componentes afectados por el cambio. (3) Las garant��as de coste obtenidas de forma autom��tica por herramientas de an��lisis est��tico no son consideradas totalmente fiables salvo que la implementaci��n de la herramienta o los resultados obtenidos sean verificados formalmente. Llevar a cabo el an��lisis de estas herramientas es una tarea tit��nica, ya que se trata de herramientas de gran tama��o y complejidad. En esta tesis nos centramos en el desarrollo de un marco formal para la verificaci��n de las garant��as de coste obtenidas por los analizadores en lugar de analizar las herramientas. Hemos implementado esta idea mediante la herramienta COSTA, un analizador de coste para programas Java y KeY, una herramienta de verificaci��n de programas Java. De esta forma, COSTA genera las garant��as de coste, mientras que KeY prueba la validez formal de los resultados obtenidos, generando de esta forma garant��as de coste verificadas. (4) Hoy en d��a la concurrencia y los programas distribuidos son clave en el desarrollo de software. Los objetos concurrentes son un modelo de concurrencia asentado para el desarrollo de sistemas concurrentes. En este modelo, los objetos son las unidades de concurrencia y se comunican entre ellos mediante llamadas as��ncronas a sus m��todos. La distribuci��n de las tareas sugiere que el an��lisis de coste debe inferir el coste de los diferentes componentes distribuidos por separado. En esta tesis proponemos un an��lisis de coste sensible a objetos que, utilizando los resultados obtenidos mediante un an��lisis de apunta-a, mantiene el coste de los diferentes componentes de forma independiente. Abstract Resource Analysis (a.k.a. Cost Analysis) tries to approximate the cost of executing programs as functions on their input data sizes and without actually having to execute the programs. While a powerful resource analysis framework on object-oriented programs existed before this thesis, advanced aspects to improve the efficiency, the accuracy and the reliability of the results of the analysis still need to be further investigated. This thesis tackles this need from the following four different perspectives. (1) Shared mutable data structures are the bane of formal reasoning and static analysis. Analyses which keep track of heap-allocated data are referred to as heap-sensitive. Recent work proposes locality conditions for soundly tracking field accesses by means of ghost non-heap allocated variables. In this thesis we present two extensions to this approach: the first extension is to consider arrays accesses (in addition to object fields), while the second extension focuses on handling cases for which the locality conditions cannot be proven unconditionally by finding aliasing preconditions under which tracking such heap locations is feasible. (2) The aim of incremental analysis is, given a program, its analysis results and a series of changes to the program, to obtain the new analysis results as efficiently as possible and, ideally, without having to (re-)analyze fragments of code that are not affected by the changes. During software development, programs are permanently modified but most analyzers still read and analyze the entire program at once in a non-incremental way. This thesis presents an incremental resource usage analysis which, after a change in the program is made, is able to reconstruct the upper-bounds of all affected methods in an incremental way. To this purpose, we propose (i) a multi-domain incremental fixed-point algorithm which can be used by all global analyses required to infer the cost, and (ii) a novel form of cost summaries that allows us to incrementally reconstruct only those components of cost functions affected by the change. (3) Resource guarantees that are automatically inferred by static analysis tools are generally not considered completely trustworthy, unless the tool implementation or the results are formally verified. Performing full-blown verification of such tools is a daunting task, since they are large and complex. In this thesis we focus on the development of a formal framework for the verification of the resource guarantees obtained by the analyzers, instead of verifying the tools. We have implemented this idea using COSTA, a state-of-the-art cost analyzer for Java programs and KeY, a state-of-the-art verification tool for Java source code. COSTA is able to derive upper-bounds of Java programs while KeY proves the validity of these bounds and provides a certificate. The main contribution of our work is to show that the proposed tools cooperation can be used for automatically producing verified resource guarantees. (4) Distribution and concurrency are today mainstream. Concurrent objects form a well established model for distributed concurrent systems. In this model, objects are the concurrency units that communicate via asynchronous method calls. Distribution suggests that analysis must infer the cost of the diverse distributed components separately. In this thesis we propose a novel object-sensitive cost analysis which, by using the results gathered by a points-to analysis, can keep the cost of the diverse distributed components separate.

An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation

Early propagation effect (EPE) is a critical problem in conventional dual-rail logic implementations against Side Channel Attacks (SCAs). Among previous EPE-resistant architectures, PA-DPL logic offers EPE-free capability at relatively low cost. However, its separate dual core structure is a weakness when facing concentrated EM attacks where a tiny EM probe can be precisely positioned closer to one of the two cores. In this paper, we present an PA-DPL dual-core interleaved structure to strengthen resistance against sophisticated EM attacks on Xilinx FPGA implementations. The main merit of the proposed structure is that every two routing in each signal pair are kept identical even the dual cores are interleaved together. By minimizing the distance between the complementary routings and instances of both cores, even the concentrated EM measurement cannot easily distinguish the minor EM field unbalance. In PA- DPL, EPE is avoided by compressing the evaluation phase to a small portion of the clock period, therefore, the speed is inevitably limited. Regarding this, we made an improvement to extend the duty cycle of evaluation phase to more than 40 percent, yielding a larger maximum working frequency. The detailed design flow is also presented. We validate the security improvement against EM attack by implementing a simplified AES co-processor in Virtex-5 FPGA.

Calibration process on the study of new antenna array architectures for space communications

This paper introduces novel calibration processes applied to antenna arrays with new architectures and technologies designed to improve the performance of traditional earth stations for satellite communications due to the increasing requirement of data capacity during last decades. Besides, the Radiation Group from the Technical University of Madrid has been working on the development of new antenna arrays based on novel architecture and technologies along many projects as a solution for the ground segment in the early future. Nowadays, the calibration process is an interesting and cutting edge research field in a period of expansion with a lot of work to do for calibration in transmission and also for reception of these novel antennas under development.

Fast magnetosonic wave excitation by an array of wires with time-modulated currents

The excitation of Fast Magnetosonic (FMS)waves by a cylindrical array of parallel tethers carrying timemodulated current is discussed. The tethers would fly vertical in the equatorial plane, which is perpendicular to the geomagnetic field when its tilt is ignored, and would be stabilized by the gravity gradient. The tether array would radiate a single FMS wave. In the time-dependent background made of geomagnetic field plus radiated wave, plasma FMS perturbations are excited in the array vicinity through a parametric instability. The growth rate is estimated by truncating the evolution equation for FMS perturbations to the two azimuthal modes of lowest order. Design parameters such as tether length and number, required power and mass are discussed for Low Earth Orbit conditions. The array-attached wave structure would have the radiated wave controlled by the intensity and modulation frequency of the currents, making an active experiment on non-linear low frequency waves possible in real space plasma conditions.

Development of a Uniform Theory of Diffraction for Scattered and Surface Electromagnetic Field Analysis on a Cylinder

Con esta tesis ���Desarrollo de una Teor��a Uniforme de la Difracci��n para el An��lisis de los Campos Electromagn��ticos Dispersados y Superficiales sobre un Cilindro��� hemos iniciado una nueva l��nea de investigaci��n que trata de responder a la siguiente pregunta: ��cu��l es la impedancia de superficie que describe una estructura de conductor el��ctrico perfecto (PEC) convexa recubierta por un material no conductor? Este tipo de estudios tienen inter��s hoy en d��a porque ayudan a predecir el campo electromagn��tico incidente, radiado o que se propaga sobre estructuras met��licas y localmente convexas que se encuentran recubiertas de alg��n material diel��ctrico, o sobre estructuras met��licas con p��rdidas, como por ejemplo se necesita en determinadas aplicaciones aeroespaciales, mar��timas o automovil��sticas. Adem��s, desde un punto de vista te��rico, la caracterizaci��n de la impedancia de superficie de una estructura PEC recubierta o no por un diel��ctrico es una generalizaci��n de varias soluciones que tratan ambos tipos de problemas por separado. En esta tesis se desarrolla una teor��a uniforme de la difracci��n (UTD) para analizar el problema can��nico del campo electromagn��tico dispersado y superficial en un cilindro circular el��ctricamente grande con una condici��n de contorno de impedancia (IBC) para frecuencias altas. Construir una soluci��n basada en UTD para este problema can��nico es crucial en el desarrollo de un m��todo UTD para el caso m��s general de una superficie arbitrariamente convexa, mediante el uso del principio de localizaci��n de los campos electromagn��ticos a altas frecuencias. Esta tesis doctoral se ha llevado a cabo a trav��s de una serie de hitos que se enumeran a continuaci��n, enfatizando las contribuciones a las que ha dado lugar. Inicialmente se realiza una revisi��n en profundidad del estado del arte de los m��todos asint��ticos con numerosas referencias. As ��, cualquier lector novel puede llegar a conocer la historia de la ��ptica geom��trica (GO) y la teor��a geom��trica de la difracci��n (GTD), que dieron lugar al desarrollo de la UTD. Despu��s, se investiga ampliamente la UTD y los trabajos m��s importantes que pueden encontrarse en la literatura. As ��, este cap��tulo, nos coloca en la posici��n de afirmar que, hasta donde nosotros conocemos, nadie ha intentado antes llevar a cabo una investigaci��n rigurosa sobre la caracterizaci��n de la impedancia de superficie de una estructura PEC recubierta por un material diel��ctrico, utilizando para ello la UTD. Primero, se desarrolla una UTD para el problema can��nico de la dispersi��n electromagn��tica de un cilindro circular el��ctricamente grande con una IBC uniforme, cuando es iluminado por una onda plana con incidencia oblicua a frecuencias altas. La soluci��n a este problema can��nico se construye a partir de una soluci��n exacta mediante una expansi��n de autofunciones de propagaci��n radial. Entonces, ��sta se convierte en una nueva expansi��n de autofunciones de propagaci��n circunferencial muy apropiada para cilindros grandes, a trav��s de la transformaci��n de Watson. De esta forma, la expresi��n del campo se reduce a una integral que se eval��a asint��ticamente, para altas frecuencias, de manera uniforme. El resultado se expresa seg��n el trazado de rayos descrito en la UTD. La soluci��n es uniforme porque tiene la importante propiedad de mantenerse continua a lo largo de la regi��n de transici��n, a ambos lados de la superficie del contorno de sombra. Fuera de la regi��n de transici��n la soluci��n se reduce al campo incidente y reflejado puramente ��pticos en la regi��n iluminada del cilindro, y al campo superficial difractado en la regi��n de sombra. Debido a la IBC el campo dispersado contiene una componente contrapolar a causa de un acoplamiento entre las ondas TEz y TMz (donde z es el eje del cilindro). Esta componente contrapolar desaparece cuando la incidencia es normal al cilindro, y tambi��n en la regi��n iluminada cuando la incidencia es oblicua donde el campo se reduce a la soluci��n de GO. La soluci��n UTD presenta una muy buena exactitud cuando se compara num��ricamente con una soluci��n de referencia exacta. A continuaci��n, se desarrolla una IBC efectiva para el c��lculo del campo electromagn��tico dispersado en un cilindro circular PEC recubierto por un diel��ctrico e iluminado por una onda plana incidiendo oblicuamente. Para ello se derivan dos impedancias de superficie en relaci��n directa con las ondas creeping y de superficie TM y TE que se excitan en un cilindro recubierto por un material no conductor. Las impedancias de superficie TM y TE est��n acopladas cuando la incidencia es oblicua, y dependen de la geometr��a del problema y de los n��meros de onda. Adem��s, se ha derivado una impedancia de superficie constante, aunque con diferente valor cuando el observador se encuentra en la zona iluminada o en la zona de sombra. Despu��s, se presenta una soluci��n UTD para el c��lculo de la dispersi��n de una onda plana con incidencia oblicua sobre un cilindro el��ctricamente grande y convexo, mediante la generalizaci��n del problema can��nico correspondiente al cilindro circular. La soluci��n asint��tica es uniforme porque se mantiene continua a lo largo de la regi��n de transici��n, en las inmediaciones del contorno de sombra, y se reduce a la soluci��n de rayos ��pticos en la zona iluminada y a la contribuci��n de las ondas de superficie dentro de la zona de sombra, lejos de la regi��n de transici��n. Cuando se usa cualquier material no conductor se excita una componente contrapolar que tiende a desaparecer cuando la incidencia es normal al cilindro y en la regi��n iluminada. Se discuten ampliamente las limitaciones de las f��rmulas para la impedancia de superficie efectiva, y se compara la soluci��n UTD con otras soluciones de referencia, donde se observa una muy buena concordancia. Y en tercer lugar, se presenta una aproximaci��n para una impedancia de superficie efectiva para el c��lculo de los campos superficiales en un cilindro circular conductor recubierto por un diel��ctrico. Se discuten las principales diferencias que existen entre un cilindro PEC recubierto por un diel��ctrico desde un punto de vista riguroso y un cilindro con una IBC. Mientras para un cilindro de impedancia se considera una impedancia de superficie constante o uniforme, para un cilindro conductor recubierto por un diel��ctrico se derivan dos impedancias de superficie. Estas impedancias de superficie est��n asociadas a los modos de ondas creeping TM y TE excitadas en un cilindro, y dependen de la posici��n y de la orientaci��n del observador y de la fuente. Con esto en mente, se deriva una soluci��n UTD con IBC para los campos superficiales teniendo en cuenta las dependencias de la impedancia de superficie. La expansi��n asint��tica se realiza, mediante la transformaci��n de Watson, sobre la representaci��n en serie de las funciones de Green correspondientes, evitando as �� calcular las derivadas de orden superior de las integrales de tipo Fock, y dando lugar a una soluci��n r��pida y precisa. En los ejemplos num��ricos realizados se observa una muy buena precisi��n cuando el cilindro y la separaci��n entre el observador y la fuente son grandes. Esta soluci��n, junto con el m��todo de los momentos (MoM), se puede aplicar para el c��lculo eficiente del acoplamiento mutuo de grandes arrays conformados de antenas de parches. Los m��todos propuestos basados en UTD para el c��lculo del campo electromagn��tico dispersado y superficial sobre un cilindro PEC recubierto de diel��ctrico con una IBC efectiva suponen un primer paso hacia la generalizaci��n de una soluci��n UTD para superficies met��licas convexas arbitrarias cubiertas por un material no conductor e iluminadas por una fuente electromagn��tica arbitraria. ABSTRACT With this thesis ���Development of a Uniform Theory of Diffraction for Scattered and Surface Electromagnetic Field Analysis on a Cylinder��� we have initiated a line of investigation whose goal is to answer the following question: what is the surface impedance which describes a perfect electric conductor (PEC) convex structure covered by a material coating? These studies are of current and future interest for predicting the electromagnetic (EM) fields incident, radiating or propagating on locally smooth convex parts of highly metallic structures with a material coating, or by a lossy metallic surfaces, as for example in aerospace, maritime and automotive applications. Moreover, from a theoretical point of view, the surface impedance characterization of PEC surfaces with or without a material coating represents a generalization of independent solutions for both type of problems. A uniform geometrical theory of diffraction (UTD) is developed in this thesis for analyzing the canonical problem of EM scattered and surface field by an electrically large circular cylinder with an impedance boundary condition (IBC) in the high frequency regime, by means of a surface impedance characterization. The construction of a UTD solution for this canonical problem is crucial for the development of the corresponding UTD solution for the more general case of an arbitrary smooth convex surface, via the principle of the localization of high frequency EM fields. The development of the present doctoral thesis has been carried out through a series of landmarks that are enumerated as follows, emphasizing the main contributions that this work has given rise to. Initially, a profound revision is made in the state of art of asymptotic methods where numerous references are given. Thus, any reader may know the history of geometrical optics (GO) and geometrical theory of diffraction (GTD), which led to the development of UTD. Then, the UTD is deeply investigated and the main studies which are found in the literature are shown. This chapter situates us in the position to state that, as far as we know, nobody has attempted before to perform a rigorous research about the surface impedance characterization for material-coated PEC convex structures via UTD. First, a UTD solution is developed for the canonical problem of the EM scattering by an electrically large circular cylinder with a uniform IBC, when it is illuminated by an obliquely incident high frequency plane wave. A solution to this canonical problem is first constructed in terms of an exact formulation involving a radially propagating eigenfunction expansion. The latter is converted into a circumferentially propagating eigenfunction expansion suited for large cylinders, via the Watson transformation, which is expressed as an integral that is subsequently evaluated asymptotically, for high frequencies, in a uniform manner. The resulting solution is then expressed in the desired UTD ray form. This solution is uniform in the sense that it has the important property that it remains continuous across the transition region on either side of the surface shadow boundary. Outside the shadow boundary transition region it recovers the purely ray optical incident and reflected ray fields on the deep lit side of the shadow boundary and to the modal surface diffracted ray fields on the deep shadow side. The scattered field is seen to have a cross-polarized component due to the coupling between the TEz and TMz waves (where z is the cylinder axis) resulting from the IBC. Such cross-polarization vanishes for normal incidence on the cylinder, and also in the deep lit region for oblique incidence where it properly reduces to the GO or ray optical solution. This UTD solution is shown to be very accurate by a numerical comparison with an exact reference solution. Then, an effective IBC is developed for the EM scattered field on a coated PEC circular cylinder illuminated by an obliquely incident plane wave. Two surface impedances are derived in a direct relation with the TM and TE surface and creeping wave modes excited on a coated cylinder. The TM and TE surface impedances are coupled at oblique incidence, and depend on the geometry of the problem and the wave numbers. Nevertheless, a constant surface impedance is found, although with a different value when the observation point lays in the lit or in the shadow region. Then, a UTD solution for the scattering of an obliquely incident plane wave on an electrically large smooth convex coated PEC cylinder is introduced, via a generalization of the canonical circular cylinder problem. The asymptotic solution is uniform because it remains continuous across the transition region, in the vicinity of the shadow boundary, and it recovers the ray optical solution in the deep lit region and the creeping wave formulation within the deep shadow region. When a coating is present a cross-polar field term is excited, which vanishes at normal incidence and in the deep lit region. The limitations of the effective surface impedance formulas are discussed, and the UTD solution is compared with some reference solutions where a very good agreement is met. And in third place, an effective surface impedance approach is introduced for determining surface fields on an electrically large coated metallic circular cylinder. Differences in analysis of rigorouslytreated coated metallic cylinders and cylinders with an IBC are discussed. While for the impedance cylinder case a single constant or uniform surface impedance is considered, for the coated metallic cylinder case two surface impedances are derived. These are associated with the TM and TE creeping wave modes excited on a cylinder and depend on observation and source positions and orientations. With this in mind, a UTD based method with IBC is derived for the surface fields by taking into account the surface impedance variation. The asymptotic expansion is performed, via the Watson transformation, over the appropriate series representation of the Green���s functions, thus avoiding higher-order derivatives of Fock-type integrals, and yielding a fast and an accurate solution. Numerical examples reveal a very good accuracy for large cylinders when the separation between the observation and the source point is large. Thus, this solution could be efficiently applied in mutual coupling analysis, along with the method of moments (MoM), of large conformal microstrip array antennas. The proposed UTD methods for scattered and surface EM field analysis on a coated PEC cylinder with an effective IBC are considered the first steps toward the generalization of a UTD solution for large arbitrarily convex smooth metallic surfaces covered by a material coating and illuminated by an arbitrary EM source.

Bit noise from an optical logic gate with laser diodes

Output bits from an optical logic cell present noise due to the type of technique used to obtain the Boolean functions of two input data bits. We have simulated the behavior of an optically programmable logic cell working with Fabry Perot-laser diodes of the same type employed in optical communications (1550nm) but working here as amplifiers. We will report in this paper a study of the bit noise generated from the optical non-linearity process allowing the Boolean function operation of two optical input data signals. Two types of optical logic cells will be analyzed. Firstly, a classical "on-off" behavior, with transmission operation of LD amplifier and, secondly, a more complicated configuration with two LD amplifiers, one working on transmission and the other one in reflection mode. This last configuration has nonlinear behavior emulating SEED-like properties. In both cases, depending on the value of a "1" input data signals to be processed, a different logic function can be obtained. Also a CW signal, known as control signal, may be apply to fix the type of logic function. The signal to noise ratio will be analyzed for different parameters, as wavelength signals and the hysteresis cycles regions associated to the device, in relation with the signals power level applied. With this study we will try to obtain a better understanding of the possible effects present on an optical logic gate with Laser Diodes.

Using array based techniques for noise source identification in cars

Una de las principales causas del ruido en nuestras ciudades es el tr��fico rodado. El ruido generado por los veh��culos no es s��lo debido al motor, sino que existen diversas fuentes de ruido en los mismos, entre las que se puede destacar el ruido de rodadura. Para localizar las causas del ruido e identificar las principales fuentes del mismo se han utilizado en diversos estudios las t��cnicas de coherencia y las t��cnicas basadas en arrays. Sin embargo, en la bibliograf��a existente, no es habitual encontrar el uso de estas t��cnicas en el sector automovil��stico. En esta tesis se parte de la premisa de la posibilidad de usar estas t��cnicas de medida en coches, para demostrar a la largo de la misma su factibilidad y su bondad para evaluar las fuentes de ruido en dos condiciones distintas: cuando el coche est�� parado y cuando est�� en movimiento. Como t��cnica de coherencia se elige la de Intensidad Selectiva, utiliz��ndose la misma para evaluar la coherencia existente entre el ruido que llega a los o��dos del conductor y la intensidad radiada por distintos puntos del motor. Para la localizaci��n de fuentes de ruido, las t��cnicas basadas en array son las que mejores resultados ofrecen. Statistically Optimized Near-field Acoustical Holography (SONAH) es la t��cnica elegida para la localizaci��n y caracterizaci��n de las fuentes de ruido en el motor a baja frecuencia. En cambio, Beamforming es la t��cnica seleccionada para el caso de media-alta frecuencia y para la evaluaci��n de las fuentes de ruido cuando el coche se encuentra en movimiento. Las t��cnicas propuestas no s��lo pueden utilizarse en medidas reales, sino que adem��s proporcionan abundante informaci��n y frecen una gran versatilidad a la hora de caracterizar fuentes de ruido. ABSTRACT One of the most important noise causes in our cities is the traffic. The noise generated by the vehicles is not only due to the engine, but there are some other noise sources. Among them the tyre/road noise can be highlighted. Coherence and array based techniques have been used in some research to locate the noise causes and identify the main noise sources. Nevertheless, it is not usual in the literature to find the application of this kind of techniques in the car sector. This Thesis starts taking into account the possibility of using this kind of measurement techniques in cars, to demonstrate their feasability and their quality to evaluate the noise sources under two different conditions: when the car is stopped and when it is in movement. Selective Intensity was chosen as coherence technique, evaluating the coherence between the noise in the driver���s ears and the intensity radiated in different points of the engine. Array based techniques carry out the best results to noise source location. Statistically Optimized Near-field Acoustical Holography (SONAH) is the measurement technique chosen for noise source location and characterization in the engine at low frequency. On the other hand, Beamforming is the technique chosen in the case of medium-high frequency and to characterize the noise sources when the car is in movement. The proposed techniques not only can be used in actual measurements, but also provide a lot of information and are very versatile to noise source characterization.

Side-Channel Attack Protection Techniques in FPGA Systems using Enhanced Dual-Rail Solutions

Esta tesis doctoral se centra principalmente en t��cnicas de ataque y contramedidas relacionadas con ataques de canal lateral (SCA por sus siglas en ingl��s), que han sido propuestas dentro del campo de investigaci��n acad��mica desde hace 17 a��os. Las investigaciones relacionadas han experimentado un notable crecimiento en las ��ltimas d��cadas, mientras que los dise��os enfocados en la protecci��n s��lida y eficaz contra dichos ataques a��n se mantienen como un tema de investigaci��n abierto, en el que se necesitan iniciativas m��s confiables para la protecci��n de la informaci��n persona de empresa y de datos nacionales. El primer uso documentado de codificaci��n secreta se remonta a alrededor de 1700 B.C., cuando los jerogl��ficos del antiguo Egipto eran descritos en las inscripciones. La seguridad de la informaci��n siempre ha supuesto un factor clave en la transmisi��n de datos relacionados con inteligencia diplom��tica o militar. Debido a la evoluci��n r��pida de las t��cnicas modernas de comunicaci��n, soluciones de cifrado se incorporaron por primera vez para garantizar la seguridad, integridad y confidencialidad de los contextos de transmisi��n a trav��s de cables sin seguridad o medios inal��mbricos. Debido a las restricciones de potencia de c��lculo antes de la era del ordenador, la t��cnica de cifrado simple era un m��todo m��s que suficiente para ocultar la informaci��n. Sin embargo, algunas vulnerabilidades algor��tmicas pueden ser explotadas para restaurar la regla de codificaci��n sin mucho esfuerzo. Esto ha motivado nuevas investigaciones en el ��rea de la criptograf��a, con el fin de proteger el sistema de informaci��n ante sofisticados algoritmos. Con la invenci��n de los ordenadores se ha acelerado en gran medida la implementaci��n de criptograf��a segura, que ofrece resistencia eficiente encaminada a obtener mayores capacidades de computaci��n altamente reforzadas. Igualmente, sofisticados cripto-an��lisis han impulsado las tecnolog��as de computaci��n. Hoy en d��a, el mundo de la informaci��n ha estado involucrado con el campo de la criptograf��a, enfocada a proteger cualquier campo a trav��s de diversas soluciones de cifrado. Estos enfoques se han fortalecido debido a la unificaci��n optimizada de teor��as matem��ticas modernas y pr��cticas eficaces de hardware, siendo posible su implementaci��n en varias plataformas (microprocesador, ASIC, FPGA, etc.). Las necesidades y requisitos de seguridad en la industria son las principales m��tricas de conducci��n en el dise��o electr��nico, con el objetivo de promover la fabricaci��n de productos de gran alcance sin sacrificar la seguridad de los clientes. Sin embargo, una vulnerabilidad en la implementaci��n pr��ctica encontrada por el Prof. Paul Kocher, et al en 1996 implica que un circuito digital es inherentemente vulnerable a un ataque no convencional, lo cual fue nombrado posteriormente como ataque de canal lateral, debido a su fuente de an��lisis. Sin embargo, algunas cr��ticas sobre los algoritmos criptogr��ficos te��ricamente seguros surgieron casi inmediatamente despu��s de este descubrimiento. En este sentido, los circuitos digitales consisten t��picamente en un gran n��mero de celdas l��gicas fundamentales (como MOS - Metal Oxide Semiconductor), construido sobre un sustrato de silicio durante la fabricaci��n. La l��gica de los circuitos se realiza en funci��n de las innumerables conmutaciones de estas c��lulas. Este mecanismo provoca inevitablemente cierta emanaci��n f��sica especial que puede ser medida y correlacionada con el comportamiento interno del circuito. SCA se puede utilizar para revelar datos confidenciales (por ejemplo, la criptograf��a de claves), analizar la arquitectura l��gica, el tiempo e incluso inyectar fallos malintencionados a los circuitos que se implementan en sistemas embebidos, como FPGAs, ASICs, o tarjetas inteligentes. Mediante el uso de la comparaci��n de correlaci��n entre la cantidad de fuga estimada y las fugas medidas de forma real, informaci��n confidencial puede ser reconstruida en mucho menos tiempo y computaci��n. Para ser precisos, SCA b��sicamente cubre una amplia gama de tipos de ataques, como los an��lisis de consumo de energ��a y radiaci��n ElectroMagn��tica (EM). Ambos se basan en an��lisis estad��stico y, por lo tanto, requieren numerosas muestras. Los algoritmos de cifrado no est��n intr��nsecamente preparados para ser resistentes ante SCA. Es por ello que se hace necesario durante la implementaci��n de circuitos integrar medidas que permitan camuflar las fugas a trav��s de "canales laterales". Las medidas contra SCA est��n evolucionando junto con el desarrollo de nuevas t��cnicas de ataque, as�� como la continua mejora de los dispositivos electr��nicos. Las caracter��sticas f��sicas requieren contramedidas sobre la capa f��sica, que generalmente se pueden clasificar en soluciones intr��nsecas y extr��nsecas. Contramedidas extr��nsecas se ejecutan para confundir la fuente de ataque mediante la integraci��n de ruido o mala alineaci��n de la actividad interna. Comparativamente, las contramedidas intr��nsecas est��n integradas en el propio algoritmo, para modificar la aplicaci��n con el fin de minimizar las fugas medibles, o incluso hacer que dichas fugas no puedan ser medibles. Ocultaci��n y Enmascaramiento son dos t��cnicas t��picas incluidas en esta categor��a. Concretamente, el enmascaramiento se aplica a nivel algor��tmico, para alterar los datos intermedios sensibles con una m��scara de manera reversible. A diferencia del enmascaramiento lineal, las operaciones no lineales que ampliamente existen en criptograf��as modernas son dif��ciles de enmascarar. Dicho m��todo de ocultaci��n, que ha sido verificado como una soluci��n efectiva, comprende principalmente la codificaci��n en doble carril, que est�� ideado especialmente para aplanar o eliminar la fuga dependiente de dato en potencia o en EM. En esta tesis doctoral, adem��s de la descripci��n de las metodolog��as de ataque, se han dedicado grandes esfuerzos sobre la estructura del prototipo de la l��gica propuesta, con el fin de realizar investigaciones enfocadas a la seguridad sobre contramedidas de arquitectura a nivel l��gico. Una caracter��stica de SCA reside en el formato de las fuentes de fugas. Un t��pico ataque de canal lateral se refiere al an��lisis basado en la potencia, donde la capacidad fundamental del transistor MOS y otras capacidades par��sitas son las fuentes esenciales de fugas. Por lo tanto, una l��gica robusta resistente a SCA debe eliminar o mitigar las fugas de estas micro-unidades, como las puertas l��gicas b��sicas, los puertos I/O y las rutas. Las herramientas EDA proporcionadas por los vendedores manipulan la l��gica desde un nivel m��s alto, en lugar de realizarlo desde el nivel de puerta, donde las fugas de canal lateral se manifiestan. Por lo tanto, las implementaciones cl��sicas apenas satisfacen estas necesidades e inevitablemente atrofian el prototipo. Por todo ello, la implementaci��n de un esquema de dise��o personalizado y flexible ha de ser tomado en cuenta. En esta tesis se presenta el dise��o y la implementaci��n de una l��gica innovadora para contrarrestar SCA, en la que se abordan 3 aspectos fundamentales: I. Se basa en ocultar la estrategia sobre el circuito en doble carril a nivel de puerta para obtener din��micamente el equilibrio de las fugas en las capas inferiores; II. Esta l��gica explota las caracter��sticas de la arquitectura de las FPGAs, para reducir al m��nimo el gasto de recursos en la implementaci��n; III. Se apoya en un conjunto de herramientas asistentes personalizadas, incorporadas al flujo gen��rico de dise��o sobre FPGAs, con el fin de manipular los circuitos de forma autom��tica. El kit de herramientas de dise��o autom��tico es compatible con la l��gica de doble carril propuesta, para facilitar la aplicaci��n pr��ctica sobre la familia de FPGA del fabricante Xilinx. En este sentido, la metodolog��a y las herramientas son flexibles para ser extendido a una amplia gama de aplicaciones en las que se desean obtener restricciones mucho m��s r��gidas y sofisticadas a nivel de puerta o rutado. En esta tesis se realiza un gran esfuerzo para facilitar el proceso de implementaci��n y reparaci��n de l��gica de doble carril gen��rica. La viabilidad de las soluciones propuestas es validada mediante la selecci��n de algoritmos criptogr��ficos ampliamente utilizados, y su evaluaci��n exhaustiva en comparaci��n con soluciones anteriores. Todas las propuestas est��n respaldadas eficazmente a trav��s de ataques experimentales con el fin de validar las ventajas de seguridad del sistema. El presente trabajo de investigaci��n tiene la intenci��n de cerrar la brecha entre las barreras de implementaci��n y la aplicaci��n efectiva de l��gica de doble carril. En esencia, a lo largo de esta tesis se describir�� un conjunto de herramientas de implementaci��n para FPGAs que se han desarrollado para trabajar junto con el flujo de dise��o gen��rico de las mismas, con el fin de lograr crear de forma innovadora la l��gica de doble carril. Un nuevo enfoque en el ��mbito de la seguridad en el cifrado se propone para obtener personalizaci��n, automatizaci��n y flexibilidad en el prototipo de circuito de bajo nivel con granularidad fina. Las principales contribuciones del presente trabajo de investigaci��n se resumen brevemente a continuaci��n: ������L��gica de Precharge Absorbed-DPL logic: El uso de la conversi��n de netlist para reservar LUTs libres para ejecutar la se��al de precharge y Ex en una l��gica DPL. ������Posicionamiento entrelazado Row-crossed con pares id��nticos de rutado en redes de doble carril, lo que ayuda a aumentar la resistencia frente a la medici��n EM selectiva y mitigar los impactos de las variaciones de proceso. ������Ejecuci��n personalizada y herramientas de conversi��n autom��tica para la generaci��n de redes id��nticas para la l��gica de doble carril propuesta. (a) Para detectar y reparar conflictos en las conexiones; (b) Detectar y reparar las rutas asim��tricas. (c) Para ser utilizado en otras l��gicas donde se requiere un control estricto de las interconexiones en aplicaciones basadas en Xilinx. ������Plataforma CPA de pruebas personalizadas para el an��lisis de EM y potencia, incluyendo la construcci��n de dicha plataforma, el m��todo de medici��n y an��lisis de los ataques. ������An��lisis de tiempos para cuantificar los niveles de seguridad. ������Divisi��n de Seguridad en la conversi��n parcial de un sistema de cifrado complejo para reducir los costes de la protecci��n. ������Prueba de concepto de un sistema de calefacci��n auto-adaptativo para mitigar los impactos el��ctricos debido a la variaci��n del proceso de silicio de manera din��mica. La presente tesis doctoral se encuentra organizada tal y como se detalla a continuaci��n: En el cap��tulo 1 se abordan los fundamentos de los ataques de canal lateral, que abarca desde conceptos b��sicos de teor��a de modelos de an��lisis, adem��s de la implementaci��n de la plataforma y la ejecuci��n de los ataques. En el cap��tulo 2 se incluyen las estrategias de resistencia SCA contra los ataques de potencia diferencial y de EM. Adem��s de ello, en este cap��tulo se propone una l��gica en doble carril compacta y segura como contribuci��n de gran relevancia, as�� como tambi��n se presentar�� la transformaci��n l��gica basada en un dise��o a nivel de puerta. Por otra parte, en el Cap��tulo 3 se abordan los desaf��os relacionados con la implementaci��n de l��gica en doble carril gen��rica. As�� mismo, se describir�� un flujo de dise��o personalizado para resolver los problemas de aplicaci��n junto con una herramienta de desarrollo autom��tico de aplicaciones propuesta, para mitigar las barreras de dise��o y facilitar los procesos. En el cap��tulo 4 se describe de forma detallada la elaboraci��n e implementaci��n de las herramientas propuestas. Por otra parte, la verificaci��n y validaciones de seguridad de la l��gica propuesta, as�� como un sofisticado experimento de verificaci��n de la seguridad del rutado, se describen en el cap��tulo 5. Por ��ltimo, un resumen de las conclusiones de la tesis y las perspectivas como l��neas futuras se incluyen en el cap��tulo 6. Con el fin de profundizar en el contenido de la tesis doctoral, cada cap��tulo se describe de forma m��s detallada a continuaci��n: En el cap��tulo 1 se introduce plataforma de implementaci��n hardware adem��s las teor��as b��sicas de ataque de canal lateral, y contiene principalmente: (a) La arquitectura gen��rica y las caracter��sticas de la FPGA a utilizar, en particular la Xilinx Virtex-5; (b) El algoritmo de cifrado seleccionado (un m��dulo comercial Advanced Encryption Standard (AES)); (c) Los elementos esenciales de los m��todos de canal lateral, que permiten revelar las fugas de disipaci��n correlacionadas con los comportamientos internos; y el m��todo para recuperar esta relaci��n entre las fluctuaciones f��sicas en los rastros de canal lateral y los datos internos procesados; (d) Las configuraciones de las plataformas de pruebas de potencia / EM abarcadas dentro de la presente tesis. El contenido de esta tesis se amplia y profundiza a partir del cap��tulo 2, en el cual se abordan varios aspectos claves. En primer lugar, el principio de protecci��n de la compensaci��n din��mica de la l��gica gen��rica de precarga de doble carril (Dual-rail Precharge Logic-DPL) se explica mediante la descripci��n de los elementos compensados a nivel de puerta. En segundo lugar, la l��gica PA-DPL es propuesta como aportaci��n original, detallando el protocolo de la l��gica y un caso de aplicaci��n. En tercer lugar, dos flujos de dise��o personalizados se muestran para realizar la conversi��n de doble carril. Junto con ello, se aclaran las definiciones t��cnicas relacionadas con la manipulaci��n por encima de la netlist a nivel de LUT. Finalmente, una breve discusi��n sobre el proceso global se aborda en la parte final del cap��tulo. El Cap��tulo 3 estudia los principales retos durante la implementaci��n de DPLs en FPGAs. El nivel de seguridad de las soluciones de resistencia a SCA encontradas en el estado del arte se ha degenerado debido a las barreras de implantaci��n a trav��s de herramientas EDA convencionales. En el escenario de la arquitectura FPGA estudiada, se discuten los problemas de los formatos de doble carril, impactos par��sitos, sesgo tecnol��gico y la viabilidad de implementaci��n. De acuerdo con estas elaboraciones, se plantean dos problemas: C��mo implementar la l��gica propuesta sin penalizar los niveles de seguridad, y c��mo manipular un gran n��mero de celdas y automatizar el proceso. El PA-DPL propuesto en el cap��tulo 2 se valida con una serie de iniciativas, desde caracter��sticas estructurales como doble carril entrelazado o redes de rutado clonadas, hasta los m��todos de aplicaci��n tales como las herramientas de personalizaci��n y automatizaci��n de EDA. Por otra parte, un sistema de calefacci��n auto-adaptativo es representado y aplicado a una l��gica de doble n��cleo, con el fin de ajustar alternativamente la temperatura local para equilibrar los impactos negativos de la variaci��n del proceso durante la operaci��n en tiempo real. El cap��tulo 4 se centra en los detalles de la implementaci��n del kit de herramientas. Desarrollado sobre una API third-party, el kit de herramientas personalizado es capaz de manipular los elementos de la l��gica de circuito post P&R ncd (una versi��n binaria ilegible del xdl) convertido al formato XDL Xilinx. El mecanismo y raz��n de ser del conjunto de instrumentos propuestos son cuidadosamente descritos, que cubre la detecci��n de enrutamiento y los enfoques para la reparaci��n. El conjunto de herramientas desarrollado tiene como objetivo lograr redes de enrutamiento estrictamente id��nticos para la l��gica de doble carril, tanto para posicionamiento separado como para el entrelazado. Este cap��tulo particularmente especifica las bases t��cnicas para apoyar las implementaciones en los dispositivos de Xilinx y su flexibilidad para ser utilizado sobre otras aplicaciones. El cap��tulo 5 se enfoca en la aplicaci��n de los casos de estudio para la validaci��n de los grados de seguridad de la l��gica propuesta. Se discuten los problemas t��cnicos detallados durante la ejecuci��n y algunas nuevas t��cnicas de implementaci��n. (a) Se discute el impacto en el proceso de posicionamiento de la l��gica utilizando el kit de herramientas propuesto. Diferentes esquemas de implementaci��n, tomando en cuenta la optimizaci��n global en seguridad y coste, se verifican con los experimentos con el fin de encontrar los planes de posicionamiento y reparaci��n optimizados; (b) las validaciones de seguridad se realizan con los m��todos de correlaci��n y an��lisis de tiempo; (c) Una t��ctica asint��tica se aplica a un n��cleo AES sobre BCDL estructurado para validar de forma sofisticada el impacto de enrutamiento sobre m��tricas de seguridad; (d) Los resultados preliminares utilizando el sistema de calefacci��n auto-adaptativa sobre la variaci��n del proceso son mostrados; (e) Se introduce una aplicaci��n pr��ctica de las herramientas para un dise��o de cifrado completa. Cap��tulo 6 incluye el resumen general del trabajo presentado dentro de esta tesis doctoral. Por ��ltimo, una breve perspectiva del trabajo futuro se expone, lo que puede ampliar el potencial de utilizaci��n de las contribuciones de esta tesis a un alcance m��s all�� de los dominios de la criptograf��a en FPGAs. ABSTRACT This PhD thesis mainly concentrates on countermeasure techniques related to the Side Channel Attack (SCA), which has been put forward to academic exploitations since 17 years ago. The related research has seen a remarkable growth in the past decades, while the design of solid and efficient protection still curiously remain as an open research topic where more reliable initiatives are required for personal information privacy, enterprise and national data protections. The earliest documented usage of secret code can be traced back to around 1700 B.C., when the hieroglyphs in ancient Egypt are scribed in inscriptions. Information security always gained serious attention from diplomatic or military intelligence transmission. Due to the rapid evolvement of modern communication technique, crypto solution was first incorporated by electronic signal to ensure the confidentiality, integrity, availability, authenticity and non-repudiation of the transmitted contexts over unsecure cable or wireless channels. Restricted to the computation power before computer era, simple encryption tricks were practically sufficient to conceal information. However, algorithmic vulnerabilities can be excavated to restore the encoding rules with affordable efforts. This fact motivated the development of modern cryptography, aiming at guarding information system by complex and advanced algorithms. The appearance of computers has greatly pushed forward the invention of robust cryptographies, which efficiently offers resistance relying on highly strengthened computing capabilities. Likewise, advanced cryptanalysis has greatly driven the computing technologies in turn. Nowadays, the information world has been involved into a crypto world, protecting any fields by pervasive crypto solutions. These approaches are strong because of the optimized mergence between modern mathematical theories and effective hardware practices, being capable of implement crypto theories into various platforms (microprocessor, ASIC, FPGA, etc). Security needs from industries are actually the major driving metrics in electronic design, aiming at promoting the construction of systems with high performance without sacrificing security. Yet a vulnerability in practical implementation found by Prof. Paul Kocher, et al in 1996 implies that modern digital circuits are inherently vulnerable to an unconventional attack approach, which was named as side-channel attack since then from its analysis source. Critical suspicions to theoretically sound modern crypto algorithms surfaced almost immediately after this discovery. To be specifically, digital circuits typically consist of a great number of essential logic elements (as MOS - Metal Oxide Semiconductor), built upon a silicon substrate during the fabrication. Circuit logic is realized relying on the countless switch actions of these cells. This mechanism inevitably results in featured physical emanation that can be properly measured and correlated with internal circuit behaviors. SCAs can be used to reveal the confidential data (e.g. crypto-key), analyze the logic architecture, timing and even inject malicious faults to the circuits that are implemented in hardware system, like FPGA, ASIC, smart Card. Using various comparison solutions between the predicted leakage quantity and the measured leakage, secrets can be reconstructed at much less expense of time and computation. To be precisely, SCA basically encloses a wide range of attack types, typically as the analyses of power consumption or electromagnetic (EM) radiation. Both of them rely on statistical analyses, and hence require a number of samples. The crypto algorithms are not intrinsically fortified with SCA-resistance. Because of the severity, much attention has to be taken into the implementation so as to assemble countermeasures to camouflage the leakages via "side channels". Countermeasures against SCA are evolving along with the development of attack techniques. The physical characteristics requires countermeasures over physical layer, which can be generally classified into intrinsic and extrinsic vectors. Extrinsic countermeasures are executed to confuse the attacker by integrating noise, misalignment to the intra activities. Comparatively, intrinsic countermeasures are built into the algorithm itself, to modify the implementation for minimizing the measurable leakage, or making them not sensitive any more. Hiding and Masking are two typical techniques in this category. Concretely, masking applies to the algorithmic level, to alter the sensitive intermediate values with a mask in reversible ways. Unlike the linear masking, non-linear operations that widely exist in modern cryptographies are difficult to be masked. Approved to be an effective counter solution, hiding method mainly mentions dual-rail logic, which is specially devised for flattening or removing the data-dependent leakage in power or EM signatures. In this thesis, apart from the context describing the attack methodologies, efforts have also been dedicated to logic prototype, to mount extensive security investigations to countermeasures on logic-level. A characteristic of SCA resides on the format of leak sources. Typical side-channel attack concerns the power based analysis, where the fundamental capacitance from MOS transistors and other parasitic capacitances are the essential leak sources. Hence, a robust SCA-resistant logic must eliminate or mitigate the leakages from these micro units, such as basic logic gates, I/O ports and routings. The vendor provided EDA tools manipulate the logic from a higher behavioral-level, rather than the lower gate-level where side-channel leakage is generated. So, the classical implementations barely satisfy these needs and inevitably stunt the prototype. In this case, a customized and flexible design scheme is appealing to be devised. This thesis profiles an innovative logic style to counter SCA, which mainly addresses three major aspects: I. The proposed logic is based on the hiding strategy over gate-level dual-rail style to dynamically overbalance side-channel leakage from lower circuit layer; II. This logic exploits architectural features of modern FPGAs, to minimize the implementation expenses; III. It is supported by a set of assistant custom tools, incorporated by the generic FPGA design flow, to have circuit manipulations in an automatic manner. The automatic design toolkit supports the proposed dual-rail logic, facilitating the practical implementation on Xilinx FPGA families. While the methodologies and the tools are flexible to be expanded to a wide range of applications where rigid and sophisticated gate- or routing- constraints are desired. In this thesis a great effort is done to streamline the implementation workflow of generic dual-rail logic. The feasibility of the proposed solutions is validated by selected and widely used crypto algorithm, for thorough and fair evaluation w.r.t. prior solutions. All the proposals are effectively verified by security experiments. The presented research work attempts to solve the implementation troubles. The essence that will be formalized along this thesis is that a customized execution toolkit for modern FPGA systems is developed to work together with the generic FPGA design flow for creating innovative dual-rail logic. A method in crypto security area is constructed to obtain customization, automation and flexibility in low-level circuit prototype with fine-granularity in intractable routings. Main contributions of the presented work are summarized next: ������Precharge Absorbed-DPL logic: Using the netlist conversion to reserve free LUT inputs to execute the Precharge and Ex signal in a dual-rail logic style. ������A row-crossed interleaved placement method with identical routing pairs in dual-rail networks, which helps to increase the resistance against selective EM measurement and mitigate the impacts from process variations. ������Customized execution and automatic transformation tools for producing identical networks for the proposed dual-rail logic. (a) To detect and repair the conflict nets; (b) To detect and repair the asymmetric nets. (c) To be used in other logics where strict network control is required in Xilinx scenario. ���������Customized correlation analysis testbed for EM and power attacks, including the platform construction, measurement method and attack analysis. ������A timing analysis based method for quantifying the security grades. ������A methodology of security partitions of complex crypto systems for reducing the protection cost. ������A proof-of-concept self-adaptive heating system to mitigate electrical impacts over process variations in dynamic dual-rail compensation manner. The thesis chapters are organized as follows: Chapter 1 discusses the side-channel attack fundamentals, which covers from theoretic basics to analysis models, and further to platform setup and attack execution. Chapter 2 centers to SCA-resistant strategies against generic power and EM attacks. In this chapter, a major contribution, a compact and secure dual-rail logic style, will be originally proposed. The logic transformation based on bottom-layer design will be presented. Chapter 3 is scheduled to elaborate the implementation challenges of generic dual-rail styles. A customized design flow to solve the implementation problems will be described along with a self-developed automatic implementation toolkit, for mitigating the design barriers and facilitating the processes. Chapter 4 will originally elaborate the tool specifics and construction details. The implementation case studies and security validations for the proposed logic style, as well as a sophisticated routing verification experiment, will be described in Chapter 5. Finally, a summary of thesis conclusions and perspectives for future work are included in Chapter 5. To better exhibit the thesis contents, each chapter is further described next: Chapter 1 provides the introduction of hardware implementation testbed and side-channel attack fundamentals, and mainly contains: (a) The FPGA generic architecture and device features, particularly of Virtex-5 FPGA; (b) The selected crypto algorithm - a commercially and extensively used Advanced Encryption Standard (AES) module - is detailed; (c) The essentials of Side-Channel methods are profiled. It reveals the correlated dissipation leakage to the internal behaviors, and the method to recover this relationship between the physical fluctuations in side-channel traces and the intra processed data; (d) The setups of the power/EM testing platforms enclosed inside the thesis work are given. The content of this thesis is expanded and deepened from chapter 2, which is divided into several aspects. First, the protection principle of dynamic compensation of the generic dual-rail precharge logic is explained by describing the compensated gate-level elements. Second, the novel DPL is originally proposed by detailing the logic protocol and an implementation case study. Third, a couple of custom workflows are shown next for realizing the rail conversion. Meanwhile, the technical definitions that are about to be manipulated above LUT-level netlist are clarified. A brief discussion about the batched process is given in the final part. Chapter 3 studies the implementation challenges of DPLs in FPGAs. The security level of state-of-the-art SCA-resistant solutions are decreased due to the implementation barriers using conventional EDA tools. In the studied FPGA scenario, problems are discussed from dual-rail format, parasitic impact, technological bias and implementation feasibility. According to these elaborations, two problems arise: How to implement the proposed logic without crippling the security level; and How to manipulate a large number of cells and automate the transformation. The proposed PA-DPL in chapter 2 is legalized with a series of initiatives, from structures to implementation methods. Furthermore, a self-adaptive heating system is depicted and implemented to a dual-core logic, assumed to alternatively adjust local temperature for balancing the negative impacts from silicon technological biases on real-time. Chapter 4 centers to the toolkit system. Built upon a third-party Application Program Interface (API) library, the customized toolkit is able to manipulate the logic elements from post P&R circuit (an unreadable binary version of the xdl one) converted to Xilinx xdl format. The mechanism and rationale of the proposed toolkit are carefully convoyed, covering the routing detection and repairing approaches. The developed toolkit aims to achieve very strictly identical routing networks for dual-rail logic both for separate and interleaved placement. This chapter particularly specifies the technical essentials to support the implementations in Xilinx devices and the flexibility to be expanded to other applications. Chapter 5 focuses on the implementation of the case studies for validating the security grades of the proposed logic style from the proposed toolkit. Comprehensive implementation techniques are discussed. (a) The placement impacts using the proposed toolkit are discussed. Different execution schemes, considering the global optimization in security and cost, are verified with experiments so as to find the optimized placement and repair schemes; (b) Security validations are realized with correlation, timing methods; (c) A systematic method is applied to a BCDL structured module to validate the routing impact over security metric; (d) The preliminary results using the self-adaptive heating system over process variation is given; (e) A practical implementation of the proposed toolkit to a large design is introduced. Chapter 6 includes the general summary of the complete work presented inside this thesis. Finally, a brief perspective for the future work is drawn which might expand the potential utilization of the thesis contributions to a wider range of implementation domains beyond cryptography on FPGAs.