Multi-wafer 3C-SiC heteroepitaxial growth on Si(100) substrates

Epitaxial growth of semiconductor films in multiple-wafer mode is under vigorous development in order to improve yield output to meet the industry increasing demands. Here we report on results of the heteroepitaxial growth of multi-wafer 3C-SiC films on Si(100) substrates by employing a home-made horizontal hot wall low pressure chemical vapour deposition (HWLPCVD) system which was designed to be have a high-throughput, multi-wafer (3x2-inch) capacity. 3C-SiC film properties of the intra-wafer and the wafer-to-wafer including crystalline morphologies, structures and electronics are characterized systematically. The undoped and the moderate NH3 doped n-type 3C-SiC films with specular surface are grown in the HWLPCVD, thereafter uniformities of intra-wafer thickness and sheet resistance of the 3C-SiC films are obtained to be 6%similar to 7% and 6.7%similar to 8%, respectively, and within a run, the deviations of wafer-to-wafer thickness and sheet resistance are less than 1% and 0.8%, respectively.

High efficiency AlxGa1-xAs/GaAs solar cells: Fabrication, irradiation and annealing effect

High efficiency AlxGa1-xAs/GaAs heteroface solar cells have been fabricated by an improved multi-wafer squeezing graphite boat liquid phase epitaxy (LPE) technique, which enables simultaneous growth of twenty 2.3 X 2.3cm(2) epilayers in one run. A total area conversion efficiency of 17.33% is exhibited (1sun, AM0, 2.0 x 2.0cm(2)). The shallow junction cell shows more resistance to 1 MeV electron radiation than the deep one. After isochronal or isothermal annealing the density and the number of deep level traps induced by irradiation are reduced effectively for the solar cells with deep junction and bombardment under high electron fluences.

Large networks of vertical multi-layer graphenes with morphology-tunable magnetoresistance

We report on the comparative study of magnetotransport properties of large-area vertical few-layer graphene networks with different morphologies, measured in a strong (up to 10 T) magnetic field over a wide temperature range. The petal-like and tree-like graphene networks grown by a plasma enhanced CVD process on a thin (500 nm) silicon oxide layer supported by a silicon wafer demonstrate a significant difference in the resistance-magnetic field dependencies at temperatures ranging from 2 to 200 K. This behaviour is explained in terms of the effect of electron scattering at ultra-long reactive edges and ultra-dense boundaries of the graphene nanowalls. Our results pave a way towards three-dimensional vertical graphene-based magnetoelectronic nanodevices with morphology-tuneable anisotropic magnetic properties. © The Royal Society of Chemistry 2013.

Multi-field simulations and characterization of CMOS-MEMS high-temperature smart gas sensors based on SOI technology

This paper describes multiple field-coupled simulations and device characterization of fully CMOS-MEMS-compatible smart gas sensors. The sensor structure is designated for gas/vapour detection at high temperatures (>300 °C) with low power consumption, high sensitivity and competent mechanic robustness employing the silicon-on-insulator (SOI) wafer technology, CMOS process and micromachining techniques. The smart gas sensor features micro-heaters using p-type MOSFETs or polysilicon resistors and differentially transducing circuits for in situ temperature measurement. Physical models and 3D electro-thermo-mechanical simulations of the SOI micro-hotplate induced by Joule, self-heating, mechanic stress and piezoresistive effects are provided. The electro-thermal effect initiates and thus affects electronic and mechanical characteristics of the sensor devices at high temperatures. Experiments on variation and characterization of micro-heater resistance, power consumption, thermal imaging, deformation interferometry and dynamic thermal response of the SOI micro-hotplate have been presented and discussed. The full integration of the smart gas sensor with automatically temperature-reading ICs demonstrates the lowest power consumption of 57 mW at 300 °C and fast thermal response of 10 ms. © 2008 IOP Publishing Ltd.

Residual Stress And Deformation Analysis Of Anodic Bonded Multi-Layer Of Glass And Aluminum

The bonding of glass wafer to aluminum foils in multi-layer assemblies was made by the common anodic bonding process. The bonding was performed at temperatures in the range 350-450 degrees C and with an applied voltage in the range 400-700 V under a pressure of 0.05 MPa. Residual stress and deformation in samples of two-layer (aluminum/glass) and three-layer (glass/aluminum/glass) were analyzed by nonlinear finite element simulation software MARC. The stress and strain varying with cooling time were obtained. The analyzed results show that deformation of the three-layer sample is significantly smaller than that of the two-layer sample, because of the symmetric structure of the three-layer sample. This has an important advantage in MEMS fabrication. The maximum equivalent stresses locate in the transition layer in both samples, which will become weakness in bonded sample.

Investigation of a chemically treated InP(100) surface during hydrophilic wafer bonding process

Surface micro-roughness, surface chemical properties, and surface wettability are three important aspects of wafer surfaces during a wafer cleaning process, which determine the bonding quality of ordinary direct wafer bonding. In this study, InP wafers are divided into four groups and treated by different chemical processes. Subsequently, the characteristics of the treated InP surfaces are carefully studied by X-ray photoelectron spectroscopy (XPS), atomic force microscopy (AFM), and contact angle measurements. The optimal wafer treatment method for wafer bonding is determined by comparing the results of the processes as a whole. This optimization is later evaluated by a scanning electronic microscope (SEM), and the ridge waveguide 1.55 mu m Si-based InP/InGaAsP multi-quantum-well laser chips are also fabricated. (c) 2005 Elsevier B.V. All rights reserved.

Very low-pressure VLP-CVD growth of high quality gamma-Al2O3 films on silicon by multi-step process

gamma-Al2O3 films were grown on Si (10 0) substrates using the sources of TMA (AI(CH3)(3)) and O-2 by very low-pressure chemical vapor deposition. The effects of temperature control on the crystalline quality, surface morphology, uniformity and dielectricity were investigated. It has been found that the,gamma-Al2O3 film prepared at a temperature of 1000degreesC has a good crystalline quality, but the surface morphology, uniformity and dielectricity were poor due to the etching reaction between 0, and Si substrate in the initial growth stage. However, under a temperature-varied multi-step process the properties Of gamma-Al2O3 film were improved. The films have a mirror-like surface and the dielectricity was superior to that grown under a single-step process. The uniformity of gamma-Al2O3 films for 2-in epi-wafer was <5%, it is better than that disclosed elsewhere. In order to improve the crystalline quality, the gamma-Al2O3 films were annealed for I h in O-2 atmosphere. (C) 2002 Elsevier Science B.V. All rights reserved.

Whole wafer magnetostriction metrology for magnetic films and multilayers

The requirements for metrology of magnetostriction in complex multilayers and on whole wafers present challenges. An elegant technique based on radius of curvature deformation of whole wafers in a commercial metrology tool is described. The method is based on the Villari effect through application of strain to a film by introducing a radius of curvature. Strain can be applied tensilely and compressively depending on the material. The design, while implemented on 3'' wafers, is scalable. The approach removes effects arising from any shape anisotropy that occurs with smaller samples, which can lead to a change in magnetic response. From the change in the magnetic anisotropy as a function of the radius, saturation magnetostriction ?s can be determined. Dependence on film composition and film thickness was studied to validate the radius of curvature approach with other techniques. ?s decreases from positive values to negative values through an increase in Ni concentration around the permalloy composition, and ?s also increases with a decrease in film thickness, in full agreement with previous reports. We extend the technique by demonstrating the technique applied to a multi-layered structure. These results verify the validity of the method and are an important step to facilitate further work in understanding how manipulation of multilayered films can offer tailored magnetostriction.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

A Multi-scale Model for Copper Dishing in Chemical-Mechanical Polishing

The present success in the manufacture of multi-layer interconnects in ultra-large-scale integration is largely due to the acceptable planarization capabilities of the chemical-mechanical polishing (CMP) process. In the past decade, copper has emerged as the preferred interconnect material. The greatest challenge in Cu CMP at present is the control of wafer surface non-uniformity at various scales. As the size of a wafer has increased to 300 mm, the wafer-level non-uniformity has assumed critical importance. Moreover, the pattern geometry in each die has become quite complex due to a wide range of feature sizes and multi-level structures. Therefore, it is important to develop a non-uniformity model that integrates wafer-, die- and feature-level variations into a unified, multi-scale dielectric erosion and Cu dishing model. In this paper, a systematic way of characterizing and modeling dishing in the single-step Cu CMP process is presented. The possible causes of dishing at each scale are identified in terms of several geometric and process parameters. The feature-scale pressure calculation based on the step-height at each polishing stage is introduced. The dishing model is based on pad elastic deformation and the evolving pattern geometry, and is integrated with the wafer- and die-level variations. Experimental and analytical means of determining the model parameters are outlined and the model is validated by polishing experiments on patterned wafers. Finally, practical approaches for minimizing Cu dishing are suggested.

Experiences with an Object-Oriented, Multi-Stage Language

Metaphor is a multi-stage programming language extension to an imperative, object-oriented language in the style of C# or Java. This paper discusses some issues we faced when applying multi-stage language design concepts to an imperative base language and run-time environment. The issues range from dealing with pervasive references and open code to garbage collection and implementing cross-stage persistence.