Comparison of the gate drive parameter space for driving power MOSFETs using conventional and cascode configurations

Conventional voltage driven gate drive circuits utilise a resistor to control the switching speed of power MOS-FETs. The gate resistance is adjusted to provide controlled rate of change of load current and voltage. The cascode gate drive configuration has been proposed as an alternative to the conventional resistor-fed gate drive circuit. While cascode drive is broadly understood in the literature the switching characteristics of this topology are not well documented. This paper explores, through both simulation and experimentation, the gate drive parameter space of the cascode gate drive configuration and provides a comparison to the switching characteristics of conventional gate drive.

Characterisation of the cascode gate drive of power MOSFETs in clamped inductive switching applications

This thesis proposes a novel gate drive circuit to improve the switching performance of MOSFET power switches in power electronic converters. The proposed topology exploits the cascode configuration, allowing the minimisation of switching losses in the presence of practical circuit constraints, which enables efficiency and power density improvements. Switching characteristics of the new topology are investigated and key mechanisms that control the switching process are identified. Unique analysis tools and techniques are also developed to demonstrate the application of the cascode gate drive circuit for switching performance optimisation.

Gate Drive Card for High Power Three Phase PWM Converters

Gate driver is an integral part of every power converter, drives the power semiconductor devices and also provides protection for the switches against short-circuit events and over-voltages during shut down. Gate drive card for IGBTs and MOSFETs with basic features can be designed easily by making use of discrete electronic components. Gate driver ICs provides attractive features in a single package, which improves reliability and reduces effort of design engineers. Either case needs one or more isolated power supplies to drive each power semiconductor devices and provide isolation to the control circuitry from the power circuit. The primary emphasis is then to provide simplified and compact isolated power supplies to the gate drive card with the requisite isolation strength and which consumes less space, and for providing thermal protection to the power semiconductor modules for 3-� 3 wire or 4 wire inverters.

Parameters influencing the performance of an IGBT gate drive

This paper presents an improvement of an IGBT gate drive implementing Active Voltage Control (AVC), and investigates the impact of various parameters affecting its performance. The effects of the bandwidths of various elements and the gains of AVC are shown in simulation and experimentally. Also, the paper proposes connecting a small Active Snubber between the IGBT collector and its gate integrated within the AVC. The effect of this snubber on enhancing the stability of the gate drive is demonstrated. It will be shown that using a wide bandwidth operational amplifier and integrating the Active Snubber within the gate drive reduces the minimum gate resistor required to achieve stability of the controller. Consequently, the response time of the IGBT to control signals is significantly reduced, the switching losses then can be minimised and, hence, the performance of gate drive as whole is improved. This reflects positively on turn-off and turn-on transitions achieving voltage sharing between the IGBTs connected in series to construct a higher voltage switch, making series IGBTs a feasible practice. ©2008 IEEE.

Dead-time minimisation using active voltage control gate drive for high-power IGBT converters

High-power converters usually need longer dead-times than their lower-power counterparts and a lower switching frequency. Also due to the complicated assembly layout and severe variations in parasitics, in practice the conventional dead-time specific adjustment or compensation for high-power converters is less effective, and usually this process is time-consuming and bespoke. For general applications, minimising or eliminating dead-time in the gate drive technology is a desirable solution. With the growing acceptance of power electronics building blocks (PEBB) and intelligent power modules (IPM), gate drives with intelligent functions are in demand. Smart functions including dead time elimination/minimisation can improve modularity, flexibility and reliability. In this paper, a dead-time minimisation using Active Voltage Control (AVC) gate drive is presented. © 2012 IEEE.

An isolated MOSFET gate driver

Traditional methods of isolated MOSFET/IGBT gate drive are presented, and their pros and cons assessed. The best options are chosen to meet our objective— a small, high speed, low cost, low power isolated gate drive module. Two small ferrite bead transformers are used for isolation, one transmits power at 2.5MHz, the other sends narrow set reset pulses. On the secondary these pulses drive a transistor totem pole to ensure high current drive, and the value is held by CMOS buffers with positive feedback. An alternative design for driving logic level devices uses only an HC buffer on the secondary. Double sided SMDconstruction (primary one side, secondary on the other) yields an upright module 40x18x5mm. Propagation delaywas 20ns, and rise/fall time 15ns with a 1nF load. The design places no limits on frequency of operation or duty cycle. Power supply requirementswere 5V@20mA for operation below 100kHz, dominated by magnetising current.

An improved gate driver for power MOSFETs using a cascode configuration

To overcome the limitations of existing gate drive topologies an improved gate drive concept is proposed to provide fast, controlled switching of power MOSFETs. The proposed topology exploits the cascode configuration with the inclusion of an active gate clamp to ensure that the driven MOSFET may be turned off under all load conditions. Key operating principles and advantages of the proposed gate drive topology are discussed. Characteristic waveforms are investigated via simulation and experimentation for the cascode driver in an inductive switching application at 375V and 10A. Experimental waveforms compared well with simulations with long gate charging delays (including the Miller plateau) being eliminated from the gate voltage waveform.

Estate of E.F. Simms, Esq....Entrance drive No. 2.

Red, black ink on linen; plans of entrance gate, drive; elevations, distances; notes indicating location, direction of photo; signed; 84 x 60 cm.; Scale: 1" = 60' [from photographic copy by Lance Burgharrdt]

Automated power semiconductor switching performance feature extraction from experimental double-pulse waveform data

Double-pulse tests are commonly used as a method for assessing the switching performance of power semiconductor switches in a clamped inductive switching application. Data generated from these tests are typically in the form of sampled waveform data captured using an oscilloscope. In cases where it is of interest to explore a multi-dimensional parameter space and corresponding result space it is necessary to reduce the data into key performance metrics via feature extraction. This paper presents techniques for the extraction of switching performance metrics from sampled double-pulse waveform data. The reported techniques are applied to experimental data from characterisation of a cascode gate drive circuit applied to power MOSFETs.

V-CE Sensing for IGBT Protection in NPC Three Level Converters-Causes For Spurious Trippings and Their Elimination

Neutral point clamped (NPC), three level converters with insulated gate bipolar transistor devices are very popular in medium voltage, high power applications. DC bus short circuit protection is usually done, using the sensed voltage across collector and emitter (i.e., V-CE sensing), of all the devices in a leg. This feature is accommodated with the conventional gate drive circuits used in the two level converters. The similar gate drive circuit, when adopted for NPC three level converter protection, leads to false V-CE fault signals for inner devices of the leg. The paper explains the detailed circuit behavior and reasons, which result in the occurrence of such false V-CE fault signals. This paper also illustrates that such a phenomenon shows dependence on the power factor of the supplied three-phase load. Finally, experimental results are presented to support the analysis. It is shown that the problem can be avoided by blocking out the V-CE sense fault signals of the inner devices of the leg.

Design Of Start-up Power Circuit For Control Power Supplies With Wide Input Voltage Variation

This paper presents the design of a start up power circuit for a control power supply (CPS) which feeds power to the sub-systems of High Power Converters (HPC). The sub-systems such as gate drive card, annunciation card, protection and delay card etc; needs to be provided power for the operation of a HPC. The control power supply (CPS) is designed to operate over a wide range of input voltage from 90Vac to 270Vac. The CPS output supplies power at a desired voltage of Vout =24V to the auxiliary sub-systems of the HPC. During the starting, the power supply to the control circuitry of CPS in turn, is obtained using a separate start-up power supply. This paper discusses the various design issues of the start-up power circuit to ensure that start-up and shut down of the CPS occurs reliably. The CPS also maintains the power factor close to unity and low total harmonic distortion in input current. The paper also provides design details of gate drive circuits employed for the CPS as well as the design of on-board power supply for the CPS. Index terms: control power supply, start-up power supply, DSFC, pre-regulator

A Simple Hysteretic Energy Harvesting Method for Nonneutral AC Switches in Load Automation

This paper presents a simple hysteretic method to obtain the energy required to operate the gate-drive, sensors, and other circuits within nonneutral ac switches intended for use in load automated buildings. The proposed method features a switch-mode low part-count self-powered MOSFET ac switch that achieves efficiency and load current THD figures comparable to those of an externally gate-driven switch built using similar MOSFETS. The fundamental operation of the method is explained in detail, followed by the modifications required for practical implementation. Certain design rules that allow the method to accommodate a wide range of single-phase loads from 10 VA to 1 kVA are discussed, along with an efficiency enhancement feature based on inherent MOSFET characteristics. The limitations and side effects of the method are also mentioned according to their levels of severity. Finally, experimental results obtained using a prototype sensor switch are presented, along with a performance comparison of the prototype with an externally gate-driven MOSFET switch.