The Architecture of Seduction: An Analysis on Digital Architectures within Consumer Society

Currently new digital tools used in architecture are often at the service of a conception of architecture as a consumer society’s cultural good. Within this neoliberal cultural frame, architects’ social function is no longer seen as the production of urban facts with sense of duty, but as a part within the symbolic logic that rules the social production of cultural values as it was defined by Veblen and developed by Baudrillard. As a result, the potential given by the new digital tools used in representation has shifted from an instrument used to verify a built project to two different main models: At the one hand the development of pure virtual architectures that are exclusively configured within their symbolic value as artistic “images” easily reproducible. On the other hand the development of all those projects which -even maintaining their attention to architecture as a built fact- base their symbolic value on the author’s image and on virtual aesthetics and logics that prevail over architecture’s materiality. Architects’ sense of duty has definitely reached a turning point.

Recapitulation in generating spatial layouts: Representations of embryogenesis in evolutionary design modelling

The noted 19th century biologist, Ernst Haeckel, put forward the idea that the growth (ontogenesis) of an organism recapitulated the history of its evolutionary development. While this idea is defunct within biology, the idea has been promoted in areas such as education (the idea of an education being the repetition of the civilizations before). In the research presented in this paper, recapitulation is used as a metaphor within computer-aided design as a way of grouping together different generations of spatial layouts. In most CAD programs, a spatial layout is represented as a series of objects (lines, or boundary representations) that stand in as walls. The relationships between spaces are not usually explicitly stated. A representation using Lindenmayer Systems (originally designed for the purpose of modelling plant morphology) is put forward as a way of representing the morphology of a spatial layout. The aim of this research is not just to describe an individual layout, but to find representations that link together lineages of development. This representation can be used in generative design as a way of creating more meaningful layouts which have particular characteristics. The use of genetic operators (mutation and crossover) is also considered, making this representation suitable for use with genetic algorithms.

Implementação Eletrônica de Sistemas Fuzzy.

Este trabalho investiga a implementação de sistemas fuzzy com circuitos eletrônicos. Tais sistemas têm demonstrado sua capacidade de resolver diversos tipos de problemas em várias aplicações de engenharia, em especial nas relacionadas com controle de processos. Para processos mais complexos, o raciocínio aproximado da lógica fuzzy fornece uma maneira de compreender o comportamento do sistema, permitindo a interpolação aproximada entre situações observadas de entrada e saída. A implementação de um sistema fuzzy pode ser baseada em hardware, em software ou em ambos. Tipicamente, as implementações em software utilizam ambientes de programação integrados com simulação, de modo a facilitar o trabalho do projetista. As implementações em hardware, tradicionais ou evolutivas, podem ser analógicas ou digitais e viabilizam sistemas de maior desempenho. Este trabalho tem por objetivo pesquisar a implementação eletrônica de sistemas fuzzy, a fim de viabilizar a criação de sistemas reais capazes de realizar o mapeamento de entrada e saída adequado. O foco é a utilização de uma plataforma com uma arquitetura analógico-digital baseada em uma tabela de mapeamento armazenada em uma memória de alta capacidade. Memórias do tipo SD (Secure Digital) foram estudadas e utilizadas na construção do protótipo eletrônico da plataforma. Também foram desenvolvidos estudos sobre a quantização, especificamente sobre a possibilidade de redução do número de bits. Com a implementação realizada é possível desenvolver um sistema fuzzy num ambiente simulado (Matlab), configurar a plataforma e executar o sistema fuzzy diretamente na plataforma eletrônica. Os testes com o protótipo construído comprovaram seu bom funcionamento.

Assistance de l’enseignement de la conception architecturale par la modélisation de savoir-faire des référents

Dans une époque de changements des moyens de représentation et communication en architecture, cette recherche porte sur l’enseignement de la conception architecturale et plus spécifiquement sur l’apport que l’informatique pourrait avoir dans ce processus. En nous basant sur une méthodologie qualitative, exploratoire et participative, nous y procédons par enchainement de questions, celle de départ étant la suivante: Comment l’enseignement de la conception architecturale pourrait tirer avantage des moyens numériques? Notre objectif est de proposer des méthodes et des outils d’apprentissage aux étudiants en architecture pour enrichir leurs démarches de conception grâce à l’ordinateur. Après une revue de la littérature dans le domaine, et un approfondissement de l’étude sur le rôle des référents architecturaux et sur la conception intégrée, nous avons procédé à une observation exploratoire du travail des étudiants en atelier d’architecture. Ces premières étapes de la recherche ont permis de dégager des discordances entre les positions théoriques et la pratique en l’atelier, pour concrétiser ultérieurement la question de recherche. Dans le but de discerner des méthodes efficaces et innovatrices pour répondre aux discordances identifiées, nous avons engagé une étude de la littérature sur les théories cognitives par rapport aux connaissances, l’apprentissage et la conception. Certaines stratégies ont pu être définies, notamment la nécessité de représentation multimodale des référents architecturaux, l’importance de représenter le processus et non seulement le résultat, ainsi que l’avantage d’inciter les étudiants à travailler dans leur ‘zone proximale’ de développement. Suite à ces recherches, une méthode d’enseignement complémentaire a été définie. Elle propose aux étudiants des explorations de l’objet en conception basées sur la manipulation des savoir-faire architecturaux. Cette méthode a été opérationnalisée d’un point de vue pédagogique ainsi que didactique et mise à l’épreuve auprès des étudiants en atelier. Un prototype de librairie de référents architecturaux interactifs (LibReArchI) a été créé dans ce but. Elle a été conçue en tant qu’environnement de conception et espace de partage de savoir-faire entre étudiants et enseignants. Les principaux résultats de cette recherche démontrent le rôle positif de la méthode proposée pour le transfert des savoir-faire architecturaux lors de l’apprentissage en atelier. Son potentiel d’assister la conception intégrée et de stimuler l’émergence d’idées a été constaté. Au niveau théorique, un modèle d’un cycle du processus de design avec le numérique a été esquissé. En conclusion, des avenues de développements futurs de cette recherche sont proposées.

Collaborative design procedures for architects and engineers

This book argues for novel strategies to integrate engineering design procedures and structural analysis data into architectural design. Algorithmic procedures that recently migrated into the architectural practice are utilized to improve the interface of both disciplines. Architectural design is predominately conducted as a negotiation process of various factors but often lacks rigor and data structures to link it to quantitative procedures. Numerical structural design on the other hand could act as a role model for handling data and robust optimization but it often lacks the complexity of architectural design. The goal of this research is to bring together robust methods from structural design and complex dependency networks from architectural design processes. The book presents three case studies of tools and methods that are developed to exemplify, analyze and evaluate a collaborative work flow.

An efficient low power FFT implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based Multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the Multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module for half-duplex operation. The results from this paper enable the baseband designers of the 200Mbit/sec variant of Multiband UWB systems (and indeed other OFDM based receivers) using System-on-Chip (SoC), FPGA and ASIC technology to create cost effective and low power solutions biased toward the competitive consumer electronics market.

A low clock frequency FFT core implementation for multiband full-rate ultra-wideband (UWB) receivers

This paper discusses the design, implementation and synthesis of an FFT module that has been specifically optimized for use in the OFDM based Multiband UWB system, although the work is generally applicable to many other OFDM based receiver systems. Previous work has detailed the requirements for the receiver FFT module within the Multiband UWB ODFM based system and this paper draws on those requirements coupled with modern digital architecture principles and low power design criteria to converge on our optimized solution particularly aimed at a low-clock rate implementation. The FFT design obtained in this paper is also applicable for implementation of the transmitter IFFT module therefore only needing one FFT module in the device for half-duplex operation. The results from this paper enable the baseband designers of the 200Mbit/sec variant of Multiband UWB systems (and indeed other OFDM based receivers) using System-on-Chip (SoC), FPGA and ASIC technology to create cost effective and low power consumer electronics product solutions biased toward the very competitive market.

Implementación y configuración de un receptor de radio definido por software (SDR) para estudios de propagación

The constant development of digital systems in radio communications demands the adaptation of the current receiving equipment to the new technologies. In this context, a new Software Defined Radio based receiver is being implemented with the aim of carrying out different experiments to analyze the propagation of signals through the atmosphere from a satellite beacon. The receiver selected for this task is the PERSEUS SDR from the Italian company Microtelecom s.r.l. It is a software defined VLF-LF-MF-HF receiver based on an outstanding direct sampling digital architecture which features a 14 bit 80 MSamples/s analog-to-digital converter, a high-performance FPGA-based digital down-converter and a high-speed 480 Mbit/s USB2.0 PC interface. The main goal is to implement the related software and adapt the new receiver to the current working environment. In this paper, SDR technology guidelines are given and PERSEUS receiver digital signal processing is presented with the most remarkable results.

FIA : an open foresic integration architecture for composing digital evidence

The analysis and value of digital evidence in an investigation has been the domain of discourse in the digital forensic community for several years. While many works have considered different approaches to model digital evidence, a comprehensive understanding of the process of merging different evidence items recovered during a forensic analysis is still a distant dream. With the advent of modern technologies, pro-active measures are integral to keeping abreast of all forms of cyber crimes and attacks. This paper motivates the need to formalize the process of analyzing digital evidence from multiple sources simultaneously. In this paper, we present the forensic integration architecture (FIA) which provides a framework for abstracting the evidence source and storage format information from digital evidence and explores the concept of integrating evidence information from multiple sources. The FIA architecture identifies evidence information from multiple sources that enables an investigator to build theories to reconstruct the past. FIA is hierarchically composed of multiple layers and adopts a technology independent approach. FIA is also open and extensible making it simple to adapt to technological changes. We present a case study using a hypothetical car theft case to demonstrate the concepts and illustrate the value it brings into the field.

Power scalable digital baseband architecture for IEEE 802.15.4

We propose a power scalable digital base band for a low-IF receiver for IEEE 802.15.4-2006. The digital section's sampling frequency and bit width are used as knobs to reduce the power under favorable signal and interference scenarios, thus recovering the design margins introduced to handle worst case conditions. We propose tuning of these knobs based on measurements of Signal and the interference levels. We show that in a 0.13u CMOS technology, for an adaptive digital base band section of the receiver designed to meet the 802.15.4 standard specification, power saving can be up to nearly 85% (0.49mW against 3.3mW) in favorable interference and signal conditions.

Low-cost digital signature architecture suitable for radio frequency identification tags

Continuing achievements in hardware technology are bringing ubiquitous computing closer to reality. The notion of a connected, interactive and autonomous environment is common to all sensor networks, biosystems and radio frequency identification (RFID) devices, and the emergence of significant deployments and sophisticated applications can be expected. However, as more information is collected and transmitted, security issues will become vital for such a fully connected environment. In this study the authors consider adding security features to low-cost devices such as RFID tags. In particular, the authors consider the implementation of a digital signature architecture that can be used for device authentication, to prevent tag cloning, and for data authentication to prevent transmission forgery. The scheme is built around the signature variant of the cryptoGPS identification scheme and the SHA-1 hash function. When implemented on 130 nm CMOS the full design uses 7494 gates and consumes 4.72 mu W of power, making it smaller and more power efficient than previous low-cost digital signature designs. The study also presents a low-cost SHA-1 hardware architecture which is the smallest standardised hash function design to date.

High performance VLSI architecture for Wave Digital Filtering

The application of fine grain pipelining techniques in the design of high performance Wave Digital Filters (WDFs) is described. It is shown that significant increases in the sampling rate of bit parallel circuits can be achieved using most significant bit (msb) first arithmetic. A novel VLSI architecture for implementing two-port adaptor circuits is described which embodies these ideas. The circuit in question is highly regular, uses msb first arithmetic and is implemented using simple carry-save adders. © 1992 Kluwer Academic Publishers.

P2P and SOA architecture for digital libraries

In an information-driven society where the volume and value of produced and consumed data assumes a growing importance, the role of digital libraries gains particular importance. This work analyzes the limitations in current digital library management systems and the opportunities brought by recent distributed computing models. The result of this work is the implementation of the University of Aveiro integrated system for digital libraries and archives. It concludes by analyzing the system in production and proposing a new service oriented digital library architecture supported in a peer-to-peer infrastructure